XMOS XK-AUDIO-316-MC-AB, Руководство по оборудованию

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xcore.ai Multichannel Audio Board 1v1 Hardware Manual
Board Net xCORE GPIO Port Description
MCLK_DIR X0D43 P8D7
Controls audio master clock direction. MCLK is an
input to xcore when low and an output when high.
EXT_PLL_SEL X0D42 P8D6
Selects which external PLL to use. CS2100 when low,
Si5351A-B-GT when high.
PLL_SYNC X0D00 P1A0 Output to CS2100 frequency reference input.
MCLK_XMOS X1D11 P1D0
Audio master clock. Input or output as specified by
MCLK_DIR and internal firmware config.
MCLK_XMOS X0D11 P1D0
Audio master clock. Input only - for use by tile0
threads e.g. USB thread for clock sync.
LRCK X1D01 P1B0 Left/Right Frame clock. Input or output.
BCLK X1D10 P1C0 Serial bit clock. Input or output.
Figure 17:
Audio clocking
GPIO
The Cirrus Logic CS2100 and Skyworks Si5351A-B-GT devices are controlled using I2C.
Further information on the xcore.ai Multichannel Audio Board I2C bus can be found in
§ 14 .
15