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73
Alarm
code
Description
Reasons
Solutions
ESC register al status code:001bh
delay value is too large.
Confirm whether there
is any problem with the
wiring of EtherCAT
communication cable
and whether there is
excessive noise on the
cable.
829
/830
Syncmanager 2/3
setting exception
protection
SM2/3 is set to an incorrect value
The physical address of SM2/3 is set incorrectly
(ESC register: 0810h/0818h): the receiving and
transmitting area overlaps, overlaps with SM2/3,
the starting address is an odd number, and the
starting address completion address is outside the
range
SM2/3 length setting (ESC register: 0812h/081a) is
different from RxPDO and TxPDO
The control register (ESC register: 0814h/081ch)
of SM2/3 is set incorrectly
ESM status after error reporting: PreOP
ESC register al status code:001dh/001eh
Set syncmanager2/3
correctly according to
ESI file description
831
PDO watchdog
setting abnormal
protection
PDO watchdog setting error
The PDO watchdog trigger is valid (SyncManager:
bit6 of register 0804h is 1), and the set value of
PDO watchdog detection timeout value (registers
0400h, 0402h) does not meet the "communication
cycle *2" condition
ESM status after error reporting: PreOP
ESC register AL status code:001fh
Correctly
set
the
watchdog
detection
timeout value
836
TxPDO
distribution
abnormal
protection
The data size of TxPDO mapping exceeds 24 bytes
ESM status after error reporting: PreOp
ESC register Al status code:0024h
Confirm that the data
size of TxPDO
mapping is set within
24 bytes
837
RxPDO
distribution
abnormal
protection
The data size of RxPDO mapping exceeds 24 bytes
ESM status after error reporting: PreOp
ESC register Al status code:0025h
Confirm that the data
size of RxPDO
mapping is set within
24 bytes
844
Synchronous
signal abnormal
protection
After the synchronization processing is completed,
the interrupt processing occurs above the set
threshold according to SYNC0 or IRQ
ESM status after error reporting: SafeOP
ESC register al status code:002Ch
Confirm the setting of
DC and whether the
propagation delay
compensation and
deviation compensation
are correct.
845
PLL does not
complete
abnormal
1s after synchronous processing, the phase
combination (PLL locking) of master station and
slave station still cannot be completed
Confirm the setting of
DC