Xilinx Zynq UltraScale+ ZCU208, Руководство пользователя

Страница: 15 / 35

Table 1: Ports
Port Name I/O Clock Description
S00_AXI AXI port S00_AXI_ACLK AXI control port
DACx_CLK In DAC AXI4-Stream clock
ADCx_CLK In ADC AXI4-Stream clock
DACxx_tdd_mode Out S00_AXI_ACLK Connect to DACxx TDD mode pin
ADCxx_tdd_mode Out S00_AXI_ACLK Connect to ADCxx TDD mode pin
Hw_trigger_en_x Out ADC AXI4-Stream clock Enable external trigger on capture block
Trigger_x Out ADC AXI4-Stream clock External trigger
Trigger_ext Out Dac0_clk External trigger for DAC
Register Map
The TDD control block register map is listed in the following table.
Table 2: Register Map
Address Description
0x0
DAC TDD mode pin, bit n: DAC channel n
0x4
ADC TDD mode pin, bit n: ADC channel n
0x8
Bit 0: reset, others: reserved
0xC
Bit 0 to 3: ADC hw_trigger_en control
0x10
Symbol to trigger on
0x14
Frame to trigger on
0x18
Arm the trigger
0x30
Tile 0 trigger delay
0x34
Tile 1 trigger delay
0x38
Tile 2 trigger delay
0x3C
Tile 3 trigger delay
0x44
Slot length (unused)
0x48
Guard band length
0x4C
Symbol length
0x50
Symbol type
Example Usage
The software commands are documented in Appendix B: Command List . The commands can be
entered into the Command log window of the RF Evaluation tool GUI (RF Data Converter Interface
User Guide (
UG1309 ). The following examples show the command sequences for DAC and ADC,
respectively.
Chapter 3: Hardware Design
UG1433 (v1.2) October 27, 2021 www.xilinx.com
RF Data Converter Evaluation Tool User Guide 15
Send Feedback