Xilinx Zynq UltraScale+ ZCU208, Руководство пользователя

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RF-DAC DDR
A DDR4 memory controller (see UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP
Product Guide (
PG150 )) is instantiated to control the external DDR4 memory. It connects to an
AXI DMA controller (see AXI DMA LogiCORE IP Product Guide ( PG021 )). The waveform loaded
into the DDR4 memory is then broadcast to the RF-DAC tiles selected by the AXI GPIO (see AXI
GPIO LogiCORE IP Product Guide (
PG144 )). The GPIO connects to the
user_select
input of the
block RAM generation and effectively bypasses this block when
user_select
is High.
For crossing clock domains, the broadcasting is done in two steps. The first step is part of the
DDR clock domain and the second step is part of the RF-DAC tile clock domain. The RF-DAC
DDR block architecture is illustrated in the following figure.
Figure 3: RF-DAC DDR Block Architecture
S_AXIS
S_AXIS1
S_AXIS2
S_AXIS3
M00_AXIS
M01_AXIS
M02_AXIS
M03_AXIS
M00_AXIS1
M01_AXIS1
M02_AXIS1
M03_AXIS1
M00_AXIS2
M01_AXIS2
M02_AXIS2
M03_AXIS2
M00_AXIS3
M01_AXIS3
M02_AXIS3
M03_AXIS3
Broadcast_stg2
M_AXIS0
M_AXIS1
M_AXIS2
M_AXIS3
M_AXIS4
M_AXIS5
M_AXIS6
M_AXIS7
M_AXIS8
M_AXIS9
M_AXIS10
M_AXIS11
M_AXIS12
M_AXIS13
M_AXIS14
M_AXIS15
S_AXIS
S_AXIS1
S_AXIS2
S_AXIS3
M_AXIS
M_AXIS1
M_AXIS2
M_AXIS3
Clock_Crossing
S_AXIS
M00_AXIS
M01_AXIS
M02_AXIS
M03_AXIS
axis_inter_dac_stg1
S01_AXI
S00_AXI
M00_AXI
broadcast_interconnect
C0_DDR4_S_AXI
dbg_clk
dbg_bus[511:0]
c0_ddr4_ul_clk_sync_rst
ddr4_0
S_AXI_LITE
M_AXI_SG
M_AXI_MM2S
M_AXIS_MM2S
axi_dma_0
S_AXI_PS_DDR
S_AXI_DMA_CTRL
AXI SmartConect (Pre-Production)
DDR4 SDRAM (MIG) (Pre-Production)
AXI4-Stream Broadcaster
(Pre-Production)
AXI Direct
Memory
Access
(Pre-Production)
S_AXI_SG_DAC
X23664-012320
RF-ADC DDR
A DDR4 memory controller (see UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP
Product Guide (
PG150 )) is instantiated to control the external DDR4 memory. The RF-ADC
output is duplicated on the output of the RF analyzer block RAM capture block. An AXI4-Stream
interconnect is then used as a switch to select which RF-ADC waveform is fed into the DMA and
captured into the DDR memory. To allow the software to control the DMA accurately, a TLAST
Chapter 3: Hardware Design
UG1433 (v1.2) October 27, 2021 www.xilinx.com
RF Data Converter Evaluation Tool User Guide 10
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