Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
406
UG586 November 30, 2016
Chapter 3:
RLDRAM II and RLDRAM 3 Memory Interface Solutions
7. Clicking
Generate Output Products
option brings up the
Manage Outputs
window
(
).
X-Ref Target - Figure 3-29
Figure 3-29:
Generate RTL and Constraints
X-Ref Target - Figure 3-30
Figure 3-30:
Generate Window