Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
188
UG586 November 30, 2016
Chapter 1:
DDR3 and DDR2 SDRAM Memory Interface Solution
contains parameters set up by the MIG tool based on the pinout selected. When
making pinout changes, Xilinx recommends rerunning the MIG tool to set up the
parameters properly. See
Bank and Pin Selection Guides for DDR3 Designs, page 193
and
Bank and Pin Selection Guides for DDR2 Designs, page 203
Mistakes to the pinout parameters can result in non-functional simulation, an unroutable
design, and/or trouble meeting timing. These parameters are used to set up the PHY and
route all the necessary signals to and from it. The following parameters are calculated based
on selected Data and Address/Control byte groups. These parameters do not consider the
system signals selection (that is, system clock, reference clock and status signals).
USER_REFRESH
This parameter indicates if the user
manages refresh commands. Can be set for
either the User or Native interface.
“ON,” “OFF”
REF_CLK_MMCM_
IODELAY_CTRL
This parameter value determines the
instantiation of MMCM. This MMCM is used
to generate 300 MHz and 400 MHz clock for
IDELAY CTRL module.
"TRUE," "FALSE"
Notes:
1. nBANK_MACHS parameter values can be changed in user_design top-level RTL file (<module name>_mig.v/vhd: This RTL file
is used as user design top RTL file for synthesis and implementation. <module name>_mig_sim.v/vhd: This RTL file is used
as user design top RTL file for simulation.). Note that the parameter value can be updated only in non-OOC MIG designs.
Table 1-65:
Embedded 7 Series FPGAs Memory Solution Configuration Parameters
(Cont’d)
Parameter
Description
Options
Table 1-66:
DDR2/DDR3 SDRAM Memory Interface Solution Pinout Parameters
Parameter
Description
Example
BYTE_LANES_B0,
BYTE_LANES_B1,
BYTE_LANES_B2
Defines the byte lanes
being used in a given I/O
bank. A 1 in a bit position
indicates a byte lane is
used, and a 0 indicates
unused. This parameter
varies based on the pinout
and should
not
be
changed manually in
generated design.
Ordering of bits from MSB to LSB is T0, T1, T2, and T3 byte
groups.
4'b1101: For a given bank, three byte lanes are used and one
byte lane is not used.
DATA_CTL_B0,
DATA_CTL_B1,
DATA_CTL_B2
Defines mode of use of
byte lanes in a given I/O
bank. A 1 in a bit position
indicates a byte lane is
used for data, and a 0
indicates it is used for
address/control. This
parameter varies based on
the pinout and should
not
be changed manually in
generated design.
4'b1100: With respect to the BYTE_LANE example, two byte
lanes are used for Data and one for Address/Control.