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Zynq-7000 PCB Design Guide

www.xilinx.com

9

UG933 (v1.8) November 7,  2014

Chapter 2:

PCB Technology Basics

Lands

For the purposes of soldering surface mount components, pads on outer layers are typically 

referred to as lands or solder lands. Making electrical connections to these lands usually 

requires vias. Due to manufacturing constraints of PTH technology, it is rarely possible to 

place a via inside the area of the land. Instead, this technology uses a short section of trace 

connecting to a surface pad. The minimum length of the connecting trace is determined by 

minimum dimension specifications from the PCB manufacturer. Microvia technology is not 

constrained, and vias can be placed directly in the area of a solder land.

Dimensions

The major factors defining the dimensions of the PCB are PCB manufacturing limits, AP SoC 

package geometries, and system compliance. Other factors such as Design For 

Manufacturing (DFM) and reliability impose further limits, but because these are 

application specific, they are not documented in this user guide.

The dimensions of the AP SoC package, in combination with PCB manufacturing limits, 

define most of the geometric aspects of the PCB structures described in this section, both 

directly and indirectly. This significantly constrains the PCB designer. The package ball pitch 

(1.0 mm for FF packages) defines the land pad layout. The minimum surface feature sizes of 

current PCB technology define the via arrangement in the area under the device. Minimum 

via diameters and keep-out areas around those vias are defined by the PCB manufacturer. 

These diameters limit the amount of space available in-between vias for routing of signals 

in and out of the via array underneath the device. These diameters define the maximum 

trace width in these breakout traces. PCB manufacturing limits constrain the minimum trace 

width and minimum spacing.

The total number of PCB layers necessary to accommodate an AP SoC is defined by the 

number of signal layers and the number of plane layers.

• The number of signal layers is defined by the number of I/O signal traces routed in and 

out of an AP SoC package (usually following the total User I/O count of the package).

• The number of plane layers is defined by the number of power and ground plane layers 

necessary to bring power to the AP SoC and to provide references and isolation for 

signal layers.

Most PCBs for large AP SoCs range from 12 to 22 layers.

System compliance often defines the total thickness of the board. Along with the number of 

board layers, this defines the maximum layer thickness, and therefore, the spacing in the Z 

direction of signal and plane layers to other signal and plane layers. Z-direction spacing of 

signal trace layers to other signal trace layers affects crosstalk. Z-direction spacing of signal 

trace layers to reference plane layers affects signal trace impedance. Z-direction spacing of 

plane layers to other plane layers affects power system parasitic inductance.

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Содержание Zynq-7000

Страница 1: ...Zynq 7000 All Programmable SoC PCB Design Guide UG933 v1 8 November 7 2014...

Страница 2: ...0402 Ceramic Capacitor subsection Deleted last sentence under Modes and Attributes Changed minimum to maximum in third sentence of second paragraph under VCCPLL PS PLL Supply Added second to last sen...

Страница 3: ...raph under Noise Limits by removing specifications and adding a reference to the data sheet Updated second paragraph under Unconnected VCCO Pins Changed Murata part number from GRM155R60J475ME47D to G...

Страница 4: ...n Lines 10 Return Currents 11 Chapter 3 Power Distribution System Introduction 12 PCB Decoupling Capacitors 12 Basic PDS Principles 17 Simulation Methods 31 PDS Measurements 32 Troubleshooting 37 Chap...

Страница 5: ...ion from XC7Z030 SBG485 to XC7Z015 CLG485 Devices Introduction 69 Differences between XC7Z030 SBG485 and XC7Z015 CLG485 Devices 69 Appendix A Additional Resources and Legal Notices Xilinx Resources 72...

Страница 6: ...ynq 7000 All Programmable SoC PCB Design Guide part of an overall set of documentation on the Zynq 7000 AP SoC is available on the Xilinx website at www xilinx com zynq Additional Support Resources Fo...

Страница 7: ...d significantly in the last few decades An insulator substrate material usually FR4 an epoxy glass composite with copper plating on both sides has portions of copper etched away to form conductive pat...

Страница 8: ...l and deforming the conductive plating These microvias cannot penetrate more than one or two layers however they can be stacked or stair stepped to form vias traversing the full board thickness Pads a...

Страница 9: ...re sizes of current PCB technology define the via arrangement in the area under the device Minimum via diameters and keep out areas around those vias are defined by the PCB manufacturer These diameter...

Страница 10: ...Transmission Lines The combination of a signal trace and a reference plane forms a transmission line All I O signals in a PCB system travel through transmission lines For single ended I O interfaces b...

Страница 11: ...nes the characteristic impedance of the transmission line formed by the trace and reference plane While interruption of reference plane continuity beneath a trace is not as dramatic in effect as sever...

Страница 12: ...AP SoC devices is listed in Table 3 1 and Table 3 2 The optimized quantities of PCB decoupling capacitors assumes that the voltage regulators have stable output voltages and meet the regulator manufac...

Страница 13: ...RAM VCCAUX VCCAUX_IO VCCO per Bank 3 4 Bank 0 680 F 330 F 100 F 4 7 F 0 47 F 100 F 47 F 4 7 F 0 47 F 47 F 4 7 F 0 47 F 47 F 4 7 F 0 47 F 47 F or 100 F 4 7 F 0 47 F 47 F CLG225 Z 7010 0 0 1 1 2 NA NA N...

Страница 14: ...7 F 100 F 47 F 4 7 F 0 47 F 47 F 4 7 F 0 47 F 47 F 4 7 F 0 47 F 47 F or 100 F 4 7 F 0 47 F 47 F Table 3 2 Required PCB Capacitor Quantities per Device PS Package Device VCCPINT VCCPAUX 1 VCCO_DDR VCCO...

Страница 15: ...CB Capacitor Quantities per Device PS Cont d Package Device VCCPINT VCCPAUX 1 VCCO_DDR VCCO_MIO0 VCCO_MIO1 VCCPLL 2 3 100 F 4 7 F 0 47 F 100 F 4 7 F 0 47 F 100 F 4 7 F 0 47 F 100 F 4 7 F 0 47 F 100 F...

Страница 16: ...es PCB Bulk Capacitors Bulk capacitors can be large and sometimes are difficult to place very close to the AP SoC Fortunately this is not a problem because the low frequency energy covered by bulk cap...

Страница 17: ...n be placed on both sides of the pads see Figure 3 1D for even lower parasitic inductance but with diminishing returns Basic PDS Principles The purpose of the PDS and the properties of its components...

Страница 18: ...g capacitors The first major component of the PDS is the voltage regulator The voltage regulator observes its output voltage and adjusts the amount of current it is supplying to keep the output voltag...

Страница 19: ...AP SoC Figure 3 3 shows a simplified PDS circuit with all reactive components represented by a frequency dependent resistor Role of Inductance Inductance is the property of the capacitors and the PCB...

Страница 20: ...parasitics in the capacitors and in all PCB current paths It is important that each of these parasitics be minimized Capacitor Parasitic Inductance The capacitance value is often considered to be a ca...

Страница 21: ...5 shows a real capacitor s impedance characteristic Overlaid on this plot are curves corresponding to the capacitor s capacitance and parasitic inductance ESL These two curves combine to form the RLC...

Страница 22: ...me multiplies the capacitance value This lowers both the high and low frequency impedance at the same time PCB Current Path Inductance The parasitic inductance of current paths in the PCB have three d...

Страница 23: ...vias per land is important with ultra low inductance capacitors such as reverse aspect ratio capacitors that place wide terminals on the sides of the capacitor body instead of the ends PCB layout eng...

Страница 24: ...determines the pair s spreading inductance The closer the spacing the thinner the dielectric the lower the spreading inductance Approximate values of spreading inductance for different thicknesses of...

Страница 25: ...arasitic via inductance in the AP SoC mounting is reduced by keeping the relevant VCC and GND planes as close to the AP SoC as possible close to the top of the PCB stackup Device pinout arrangement de...

Страница 26: ...ses the vertical distance VCC and GND via length that currents travel before reaching the associated VCC and GND planes To reduce spreading inductance every VCC plane should have an adjacent GND plane...

Страница 27: ...inductance plus the inductance of the vias planes and connecting traces between the capacitor and the AP SoC The capacitor s self resonant frequency FRSELF capacitor data sheet value is much higher th...

Страница 28: ...of the curve the capacitors are equally effective Capacitor Anti Resonance One problem associated with combinations of capacitors in a PDS of an AP SoC is anti resonant spikes in the PDS aggregate imp...

Страница 29: ...itor s effectiveness For a capacitor to be effective in providing transient current at a certain frequency for example the capacitor s resonant frequency the phase relationship based on the distance t...

Страница 30: ...the decoupling capacitors Moving away from the device in concentric rings the termination resistors and transceiver supply filtering should be closest to the device followed by the smallest value dec...

Страница 31: ...e without using a fairly sophisticated simulator and taking a significant amount of time Basic lumped RLC simulation is one of the simplest simulation methods Though it does not account for the distri...

Страница 32: ...connect directly to the VCC and GND vias with surface traces These capacitors confuse the measurement by acting like a short circuit for the high frequency AC current To make sure the measurements ar...

Страница 33: ...ggressor are removed through averaging Power system noise measurements should be made at a few different AP SoC locations to ensure that any local noise phenomena are captured Figure 3 8 shows an aver...

Страница 34: ...the oscilloscope however many of these functions do not have resolution sufficient to give a clear picture of the noise spectrum Alternatively a long sequence of time domain data can be captured from...

Страница 35: ...A spectrum analyzer takes its measurements using a 50 cable instead of an active probe A good method attaches the measurement cable through a coaxial connector tapped into the power and ground planes...

Страница 36: ...zer or an oscilloscope with FFT The power system impedance can be determined either through direct measurement or simulation or a combination of these two as there are often many variables and unknown...

Страница 37: ...oise are measured locally at these devices the local PDS and the component decoupling networks should be analyzed Possibility 2 Parasitic Inductance of Planes Vias or Connecting Traces Sometimes the d...

Страница 38: ...diodes injecting current into the VCCO PDS If large amounts of noise are present on VCCO the drive strength of these interfaces should be decreased or different termination should be used on input or...

Страница 39: ...choose I O interface standards and optimize them according to the purpose of the system This chapter contains the following sections Interface Types Single Ended Signaling Interface Types To better ad...

Страница 40: ...Rate SDR and Double Data Rate DDR interfaces has to do with the relationship of the data signals of a bus to the clock signal of that bus In SDR systems data is only registered at the input flip flop...

Страница 41: ...er which reduces the need for a large voltage swing of the signal at the input receiver Two 1 8V I O standards that illustrate this are LVCMOS18 and SSTL18 Class 1 The thresholds for 1 8V LVCMOS are s...

Страница 42: ...lly refers to impedance matching or impedance compensating devices that are used to maintain signal integrity in an interface While many types of elements can be used as terminators such as resistors...

Страница 43: ...utput impedance approximately equal to 50 Figure 4 3 Typically parallel terminations have best performance when VTT the voltage source connected to the parallel termination resistor is equal to half o...

Страница 44: ...tion topology Other standards might not have any hard requirements but rather might simply provide examples of termination topologies An example of a standard with specific termination requirements is...

Страница 45: ...only applicable termination type for this topography The second critical aspect is the length of the connecting stubs at each receiver These must remain short no more than a fraction of a signal rise...

Страница 46: ...are required to assess signal integrity at the individual receivers Table 4 2 lists example I O interface types that can be used with the unidirectional multi drop topography LVTTL and LVCMOS do not s...

Страница 47: ...termination Figure 4 8 is rarely appropriate for bidirectional interfaces as incoming signals are attenuated by the series resistor of the receiving transceiver Parallel termination Figure 4 7 almost...

Страница 48: ...a driver output impedance of 25 50 parallel terminations are appropriate Figure 4 7 Controlled impedance drivers whether implemented with DCI or with weak LVCMOS drivers should be sized to have an ou...

Страница 49: ...vailable it is advisable to use a Thevenin parallel termination Thevenin parallel termination consists of a voltage divider with a parallel resistance equal to the characteristic impedance of the tran...

Страница 50: ...vers target to have output impedances close to 40 50 better signal integrity can be achieved without any external source series termination When possible it is a better starting point to consider the...

Страница 51: ...logic circuits This supply can be combined with VCCINT if the system does not require the PL supply to be powered down independent of the PS VCCPAUX PS Auxiliary Logic Supply VCCPAUX is a 1 8V nominal...

Страница 52: ...ully managed The recommended connection between the 10 F 0603 capacitor and the VCCPLL BGA ball is a planelet with a minimum width of 80 mil 2 mm and a length of less than 3 000 mil 76 mm If a planele...

Страница 53: ...ovide a voltage reference for the PS_DDR_DQ and PS_DDR_DQS input receivers They need to be tied to a termination voltage Vtt equal to VCCO_DDR 2 For example for DDR3 VCCO_DDR is set to 1 5V then VREF...

Страница 54: ...ll down pull up resistors Unused DDR Memory When no PS DDR memory is used VCCO_DDR should be tied to VCCPAUX PS_DDR_VREF0 1 and PS_DDR_VRN P should be left floating PS MIO Power Supplies VCCO_MIO0 PS...

Страница 55: ...used to generate PS_MIO_REF A 0 01 F capacitor shall be added for decoupling If RGMII is not being used PS_MIO_VREF is safe to float Power Sequencing Refer to DS187 Zynq 7000 All Programmable SoC Z 7...

Страница 56: ...ignal that is mostly used for debugging proposes PS_SRST_B must be High to begin the boot process If PS_SRST_B is not used it can be pulled High to VCCO_MIO1 Boot Mode Pin MIO 8 MIO 8 is used to confi...

Страница 57: ...the recommendations for DDR memory designs for Zynq 7000 AP SoC devices DDR Interface Signal Pins Table 5 4 lists all dynamic memory interface signals in Bank 502 X Ref Target Figure 5 4 Figure 5 4 Se...

Страница 58: ...DDR_DQ 31 0 I O Data DDR_DM 3 0 O Data mask DDR_DQS_P 3 0 I O Differential data strobe positive DDR_DQS_N 3 0 I O Differential data strobe negative DDR_VRP I O Used to calibrate input termination DDR...

Страница 59: ..._b ras_b cas_b odt cs_b Addr Command Contrl Addr we_b ras_b cas_b odt cs_b Addr Command Contrl Addr we_b ras_b cas_b odt cs_b VREF VDDQ VREF VDDQ VREF VDDQ VREF VDDQ VREF VDDQ VREF VDDQ VREF VDDQ VTT...

Страница 60: ...ontrl Addr we_b ras_b cas_b cs_b Addr Command Contrl Addr we_b ras_b cas_b odt cs_b Addr Command Contrl Addr we_b ras_b cas_b odt cs_b cke cke cke cke Addr Command Contrl Addr we_b ras_b cas_b odt cs_...

Страница 61: ...y decoupling capacitor is recommended for each IC If a regulator is used a low impedance plane or planelet is recommended for distribution X Ref Target Figure 5 7 Figure 5 7 LPDDR2 Board Implementatio...

Страница 62: ...gth All DDR memory devices should be placed as closely to the Zynq 7000 AP SoC device as possible Table 5 8 shows the maximum recommended trace lengths for DDR signals VTT VDDQ 2 VDDQ 2 VDDQ 2 VDDQ 2...

Страница 63: ...e the CK trace to be equal to or longer than the DQS trace per byte lane DDR Trace Impedance All DDR signals except DDR_DRST_B require controlled impedance DDR_CKE also requires controlled impedance i...

Страница 64: ...20 mm Table 5 12 shows the recommended routing topologies Byte and bit swapping is allowed to facilitate PCB routing except for LPDDR2 which specifically forbids swapping When swapping bits keep all...

Страница 65: ...ithout internal delays Requires clock to be delayed using longer PCB routes by 1 5 ns 2 0 ns with respect to average delay of DATA 3 0 and CTL Delay skew for DATA 3 0 and CTL should be less than 100 p...

Страница 66: ...en operating the TPIU in MIO mode the trace clock output should be delayed by approximately one half clock period This can be done on the PCB or by the debugging device ARM_DSTREAM Lauterbach Agilent...

Страница 67: ...ent of the Zynq 7000 AP SoC device In other words TQSPICKD Tckominflash 2 Tpd requirement For example with a Zynq 7000 AP SoC hold time requirement of 1 3 ns and a flash clock to out of 1 0 ns the pro...

Страница 68: ...minimum clock to out time of the Zynq 7000 device Using data from DS191 and a popular flash vendor s data sheet the effect of trace delay on the maximum frequency can be illustrated As can be seen fr...

Страница 69: ...e two devices needs to be aware of these differences Differences between XC7Z030 SBG485 and XC7Z015 CLG485 Devices When migrating from an XC7Z030 SBG485 device to an XC7Z015 CLG485 device some key dif...

Страница 70: ...argeting maximum performance PCB and system simulations are crucial to determine if system wide timing can be met There are also a number of pinout differences between the two packages as noted in Tab...

Страница 71: ...0 SBG485 device Software Considerations The Zynq 7000 XC7Z015 device is not supported in the ISE Design Suite and you should not use the Zynq 7000 XC7Z030 device in the SBG485 package in an attempt to...

Страница 72: ...Answer Record to your myAlerts Device User Guides http Zynq 7000 AP SoC Product Page http www xilinx com products silicon devices soc zynq 7000 index htm Xilinx Design Tools Release Notes Installation...

Страница 73: ...ics Data Sheet UG865 Zynq 7000 All Programmable SoC Packaging and Pinout Specifications UG821 Zynq 7000 All Programmable SoC Software Developers Guide UG585 Zynq 7000 All Programmable SoC Technical Re...

Страница 74: ...ce on the AXI protocol Software Documents UG821 Zynq 7000 All Programmable SoC Software Developers Guide UG873 Zynq 7000 All Programmable SoC Concepts Tools and Techniques CTT The source drivers for s...

Страница 75: ...ace standards refer the following documents Note ARM documents can be found at http infocenter arm com help index jsp ARM AMBA Level 2 Cache Controller L2C 310 TRM also called PL310 ARM AMBA Specifica...

Страница 76: ...00 Final 070130 SD Association Part E1 SDIO Specification Ver2 00 Final 070130 SD Group Part 1 Physical Layer Specification Ver2 00 Final 060509 Please Read Important Legal Notices The information dis...

Страница 77: ...performance you assume sole risk and liability for use of Xilinx products in such critical applications please refer to Xilinx s Terms of Sale which can be viewed at http www xilinx com legal htm tos...

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