Xilinx Virtex-II Pro PPC405, Руководство пользователя

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March 2002 Release www.xilinx.com 493
Virtex-II Pro™ Platform FPGA Documentation 1-800-255-7778
PPC405D5 Exceptions and Interrupts
R
Referring to Figure 7-1 , the actions performed by the processor when an interrupt occurs
are:
1. Save the interrupt-return address (effective address).
Generally, the return address is either that of the instruction that caused the exception,
or the next-sequential instruction that would have executed had no exception
occurred. It is saved in one of two save/restore registers, depending on the type of
interrupt:
- Critical interrupts load SRR2 with the return address.
- Noncritical interrupts load SRR0 with the return address.
Refer to the specific interrupt description in Interrupt Reference , page 502 for
information on the saved return address.
2. Save the interrupted-program state.
Figure 7-1: PPC405 Exception Mechanism
UG011_46_033101
Data Storage 0x0300
Alignment 0x0600
External 0x0500
Instruction Storage 0x0400
Program 0x0700
System Call 0x0C00
Programmable-Interval Timer 0x1000
Fixed-Interval Timer 0x1010
Data TLB Miss 0x1100
Instruction TLB Miss 0x1200
Critical Input 0x0100
Machine Check 0x0200
Watchdog Timer 0x1020
Debug 0x2000
DEAR
ESR
Update
Update
EVPR
Interrupt-Handler
Table
Physical Memory
Noncritical Exceptions
Critical Exceptions
Exception-Vector Offset
+
64KB
Boundary
New Machine State
Interrupt
Return Address
SRR2
MSR
SRR3
Old Machine State
New Machine State
Interrupt
Return Address
SRR0
MSR
SRR1
Old Machine State