Virtex-6 FPGA Connectivity Kit Getting Started
59
UG664 (v1.4) July 6, 2011
Next Steps
Packet DMA
shows the design module for Packet DMA.
shows the design file
structure.
X-Ref Target - Figure 54
Figure 54:
Packet DMA Design Module
X-Ref Target - Figure 55
Figure 55:
Packet DMA Design FIles
UG664_1
8
_051911
P
a
cket
DMA
C2
S
S
2C
C2
S
S
2C
64-
b
it AXI4-
S
tre
a
m B
as
ic Interf
a
ce @ 250 MHz
Regi
s
ter
Interf
a
ce
S
2C_Ctrl
S
2C_D
a
t
a
64
C2
S
_Ctrl
C2
S
_D
a
t
a
@250 MHz
@250 MHz
S
2C_Ctrl
S
2C_D
a
t
a
64
C2
S
_Ctrl
C2
S
_D
a
t
a
UG664_19_090
8
10
v6_pcie_10Gdm
a
_ddr
3
_x
au
i_
a
xi
de
s
ign
ip_core
s
dm
a
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