Virtex-5 LXT/SXT/FXT FPGA Prototype Platform
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17
UG229 (v3.0.1) May 21, 2008
Detailed Description
R
4. JTAG Chain
J41 is a 2 x 3 header (
Figure 4
) that allows users to select either the ISPROM or the FPGA or
both devices in the JTAG chain.
Table 5
shows the jumper settings for the JTAG chain
header.
5. JTAG Termination Header
When connecting another board to the downstream System ACE interface connector (P3)
or the downstream interface connector (P4), jumper pins 1-2 on the JTAG termination
header (J22); otherwise jumper pins 2-3 for on-board termination.
The TCK and TMS pins are parallel feedthrough connections from the upstream
System ACE interface connector to the downstream System ACE interface connector and
drive the TCK and TMS pins of the onboard PROM and the DUT.
Note:
The termination jumper must be in place on the last board in the chain to connect the TDO pin
of the final device to the TDO feedback chain.
X-Ref Target - Figure 4
Figure 4:
JTAG Chain Jumper
Table 5:
J41 Jumper Settings
J41 Pin Jumpers
PROM JTAG
FPGA JTAG
1-3
Enable
3-5
Disable
2-4
Enable
4-6
Disable
UG229_04_050407
1
J41
PROM_TDO
FPGA_TDO
ON_BOARD_TDO
TDI
3
5
2
4
6
