Xilinx Virtex-4 ML455, Руководство пользователя

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Virtex-4 ML455 PCI/PCI-X Board www.xilinx.com 13
UG084 (v1.0) May 17, 2005
Clock Generation
R
Clock Generation
The clock generation section of the ML455 board provides three clock sources:
1. Epson EG-2121CA-200.0000M-PHPA 2.5V LVPECL (differential) oscillator
♦
200 MHz Virtex-4 FPGA IDELAY reference clock.
2. Epson EG-2121CA-133.0000M-LHPA 2.5V LVDS (differential) oscillator
♦
133 MHz clock for PCI-X designs and DDR SDRAM memory interface.
3. Epson SG-8002CA-33.0000M-PCC 3.3V LVCMOS (single-ended) oscillator
♦
This oscillator is an optional configuration oscillator for Platform Flash (U1). This
clock is buffered via U9.
Table 3-1 lists the destination pins of these clock sources.
The PCI specification calls for the PCI bus clock, sourced from the motherboard PCI slot, to
have one load on the add-in cards. The Xilinx PCI and PCI-X IP cores, depending upon bus
mode and frequency, require that the PCI bus clock enter the FPGA on a specific clock pin
(refer to
Table 1-1 ).
The ML455 board PCI bus clock is implemented as follows:
•
The PCI bus clock (signal CLK_FROM_EDGE) enters the board on PCI edge
connector P1 pin B16.
•
The clock is then routed in a “Y” topology to two parallel 0
Ω
resistors, R2 and R242.
•
The output side of R2 (signal PCIBUSCLK1) is routed to FPGA pin C13 (the global
clock pin of FPGA).
•
The output side of R242 (signal PCIBUSCLK2) is routed to FPGA pin D2 (the regional
clock pin of FPGA).
•
The total length of each clock trace (including the length of the 0
Ω
resistor) from pin
P1.16 to its FPGA pin is 2.5 inches.
Refer to Appendix A, “PCI Bus Clock Simulations,” for 133 MHz clock waveforms at the
FPGA clock pins C13 and D2, with different R2 and R242 configurations.
If full electrical compliance is required, the designer has the option to remove one of the
two 0 ohm resistors (R2 or R242). As shipped, the ML455 board has both resistors installed
and works with all versions of the Xilinx PCI/PCI-X LogiCORE cores.
Table 3-1: ML455 Board Clock Sources
Clock
Designator
Output Type Frequency Destination Pin
Y1 Differential LVPECL 200 MHz FPGA U10 Bank 4 AE14 (P)
FPGA U10 Bank 4 AE13 (N)
Y2 Differential LVDS 133 MHz FPGA U10 Bank 4 AD12 (P)
FPGA U10 Bank 4 AD11 (N)
Y3 Single-ended LVCMOS 33 MHz Clock Buffer U9 input pin 1 (P)
U9 pin 8 Single-ended LVCMOS 33 MHz FPGA U10 Bank 3 B15 (P)
P1 pin B15 Single-ended PCI 3.3V 33 MHz to
133 MHz
FPGA U10 Bank 3 C13 (P) and
FPGA U10 Bank 6 D2 (P)
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