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Spartan-3A

/3AN

Starter Kit Board

Differential I/O Headers

2x1

stake pin header

2x1

stake pin header

FPGA

Bank 2

FPGA

Bank 0

Pairs of pins on the

header form potential

differential I/O pairs.

Optionally, each pin

can be a single-ended

I/O pin.

Transmit

Receive

Recieve stake pins

Transmit stake pins

Each individual

differential I/O pair

is routed with matched

100-ohm impedance.

If using differential inputs, set the DIFF_TERM=TRUE constraint.

There are no external termination resistors provided on the board.

INST <I/O_BUFFER_INSTANTIATION_NAME> DIFF_TERM = “TRUE” ;

The receive clock differential

pair feeds the GCLK6 and

GCLK7 global clock inputs,

which in turn connect to the

DCM_X2Y3

top, right DCM labeled

Содержание Spartan-3A DSP FPGA Series

Страница 1: ...an 3A 3AN Starter Kit Board Schematic Annotated 21 AUG 2007 For additional information www xilinx com s3astarter See UG334 Spartan 3A 3AN Starter Kit User Guide for further information on each board feature ...

Страница 2: ...r 6 pin Headers Hirose FX2 100 pin Expansion Connector Connectorless Debugging Port Landing Pads Six pin Accesory Headers DAC Analog Outputs ADC Analog Inputs FX2 Expansion Connector Six pin Accessory Headers Connectorless Debugging Port ADC Inputs DAC Outputs ...

Страница 3: ...232 serial ports 12 bit VGA port SPI PROM select jumpers VGA PS 2 Audio jack Clock SMA SPI select jumper RS 232 DCE DTE The PS 2 connector has primary and secondary connections to the FPGA The secondary connections are available by attaching an external Y splitter cable Primary DATA Secondary DATA Primary CLK Secondary CLK NOTE See schematic Page 13 for details ...

Страница 4: ...Spartan 3A 3AN Starter Kit Board TM 10 100 Ethernet PHY magnetics RJ 45 Connector LAN8700 10 100 Ethernet PHY www smsc com main catalog lan8700 html LAN8700 10 100 Ethernet PHY RJ 45 Connector ...

Страница 5: ... Banks 0 1 2 FPGA auxiliary supply Embedded USB JTAG Programmer Bank 0 Bank 2 Bank 1 Bank 3 1 2V 3 3V 3 3V 1 8V FPGA FPGA DDR2 SDRAM Termination 0 9V DDR2 SDRAM Device FPGA 1 8V DAC Reference Voltage 3 3V DDR2 SDRAM Voltage Ref 0 9V I C Interface 2 I C Interface 2 regulators Power switch Wall power adapter input I O Bank 3 ...

Страница 6: ...n PROG_B pushbutton SUSPEND switch JTAG Header Platform Flash PROM Jumper J26 M0 M1 M2 J26 Master Serial M0 M1 M2 J26 Master SPI M0 M1 M2 J26 Master BPI M0 M1 M2 J26 JTAG M0 M1 M2 J26 Master Internal SPI Platform Flash Enable Jumper Jumper J46 Spartan 3AN only DONE CE GND J46 PROM DONE CE GND J46 PROM DONE CE GND J46 PROM Platform Flash Enable Jumper Jumper J46 DISABLE Enable only during configura...

Страница 7: ...AN Starter Kit Board TM FPGA I O Bank 0 and Bank 1 Clock Oscillators 50 MHz Oscillator Auxiliary Oscillator Socket CLK_50MHZ CLK_AUX FPGA Bank 1 FPGA Bank 0 FPGA XC3S700A AN 4FGG484C E FPGA XC3S700A AN 4FGG484C ES ...

Страница 8: ...A AN Starter Kit Board TM FPGA I O Bank 2 and Bank 3 FPGA FPGA Bank 2 Bank 3 AWAKE LED FPGA I O Bank 3 is dedicated to the DDR2 SDRAM interface interface FPGA XC3S700A AN 4FGG484C ES FPGA XC3S700A AN 4FGG484C ES ...

Страница 9: ...Spartan 3A 3AN Starter Kit Board TM FPGA Power Supply Decoupling ...

Страница 10: ...l 12 bit resolution serial www linear com pc productDetail do navId H0 C1 C1155 C1005 C1156 P2048 3 3V nominally 3 3V The DAC_REF_CD voltage is programmable via the I2C control interface on the LP3906 voltage regulator designated as IC18 on sheet 5 At power up this reference voltage is 3 3V see sheet 2 Thevenin termination to improve the signal integrity on these high fanout signals Programmable G...

Страница 11: ... software See the DDR SDRAM chapter in UG334 Spartan 3A 3AN Starter Kit User Guide 0Ω DESIGN NOTE The Revision C board has an inductor in this location Shorting across this location improves high frequency DDR2 SDRAM interface performance The Revision D board uses a 0Ω resistor DESIGN NOTE The Revision C board has an inductor in this location Shorting across this location improves high frequency D...

Страница 12: ...x8 x16 parallel NOR Flash www st com stonline products families memories fl_nor_emb fl_m29dw htm To configure from parallel NOR Flash remove Jumper J46 to disable the Platform Flash PROM M0 M1 M2 J26 DONE CE GND J46 PROM To configure from parallel NOR Flash set the FPGA mode select pins using Jumper J46 as shown ...

Страница 13: ... architecture However only one STMicro and one Atmel PROM are mounted on the board www atmel com products DataFlash Jumper J1 J1 J1 DONE CE GND J46 PROM Platform Flash Jumper Jumper J46 Jumper J1 defines which SPI Flash is used for SPI mode configuration and which is available using a second SPI slave select signal Configure From Atmel Select Signal STMicro Select Signal M0 M1 M2 J26 Atmel STMicro...

Страница 14: ...itches discrete LEDs Rotary knob switch with pushbutton switch Eight discrete LEDs Four pushbutton switches Four slide switches 16 character by 2 line LCD display Four pushbutton switches surround rotary knob Rotary pushbutton switch Four slide switches Eight discrete LEDs 16x2 character LCD ...

Страница 15: ...DRAM Termination Network 1 of 2 The DDR2 SDRAM interface has specific pin assignment and layout requirements to support the Xilinx Memory Interface Generator MIG software See the DDR SDRAM chapter in UG334 Spartan 3A 3AN Starter Kit User Guide ...

Страница 16: ...DRAM Termination Network 2 of 2 The DDR2 SDRAM interface has specific pin assignment and layout requirements to support the Xilinx Memory Interface Generator MIG software See the DDR SDRAM chapter in UG334 Spartan 3A 3AN Starter Kit User Guide ...

Страница 17: ...smit Receive Recieve stake pins Transmit stake pins Each individual differential I O pair is routed with matched 100 ohm impedance If using differential inputs set the DIFF_TERM TRUE constraint There are no external termination resistors provided on the board INST I O_BUFFER_INSTANTIATION_NAME DIFF_TERM TRUE The receive clock differential pair feeds the GCLK6 and GCLK7 global clock inputs which in...

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