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PCI32 Interface v3.0

DS206 August 31, 2005

www.xilinx.com

3

Product Specification v3.0.151

Notes 

1. Spartan-3 and Spartan-3E solution pending production speed files.
2. For additional Part/Package combinations, see the UCF Generator in the PCI Lounge.
3. XC2V1000 is supported over Military Temp. range
4. Spartan-3, Spartan-3E, and Virtex-4 devices do not contain TBUFs. The Xilinx tools automatically translate TBUFs to LUTs, 

and they are included in the worst case LUT count listed.

5. Virtex-II Pro, Virtex-4, Spartan-3, and Spartan-3E devices are supported over commercial and industrial temperature ranges.
6. As shipped, the core is verified for timing compliance with speedfile versions 1.56 and later. This applies to all production 

devices and most engineering samples. If you are using engineering samples that require the 1.54 speedfile, please contact 
Xilinx Customer Applications..

7. Requires 200 MHz reference clock.

Applications

• Embedded applications in networking, industrial, and telecommunication systems

• PCI add-in boards such as frame buffers, network adapters, and data acquisition boards

• Hot swap CompactPCI boards

• CardBus compliant

• Any applications that need a PCI interface

General Description

The Xilinx PCI interface is a pre-implemented and fully tested module for Xilinx FPGAs. The pinout for
each device and the relative placement of the internal logic are predefined. Critical paths are controlled
by constraints and guide files to ensure predictable timing. This significantly reduces engineering time
required to implement the PCI portion of your design. Resources can instead be focused on your
unique user application logic in the FPGA and on the system-level design. As a result, Xilinx PCI prod-
ucts minimize your product development time.

The core meets the setup, hold, and clock-to-timing requirements as defined in the PCI specification.
The interface is verified through extensive simulation.

Spartan

-II XC2S30-PQ208-5C

3.3V, 5.0V only

Spartan-II XC2S50-PQ208-5C

3.3V, 5.0V only

Spartan-II XC2S100-PQ208-5C

3.3V, 5.0V only

Spartan-II XC2S150-PQ208-5C

3.3V, 5.0V only

Spartan-II XC2S200-PQ208-5C

3.3V, 5.0V only

Spartan-IIE 2S50E-PQ208-6C

3.3V only

Spartan-IIE XC2S100E-PQ208-6C

3.3V only

Spartan-IIE XC2S150E-PQ208-6C

3.3V only

Spartan-IIE XC2S200E-PQ208-6C

3.3V only

Spartan-IIE XC2S300E-PQ208-6C

3.3V only

Spartan-3 XC3S1000-FG456-4C/I 

(1)

3.3V only

Spartan-3E XC3S1200E-FG400-4C/I

3.3V only

Table  1:  

Core Implementation 

(Continued)

 

Supported Device

Power Supply

Содержание PCI32

Страница 1: ...dBus compliant Supported initiator functions Configuration read configuration write Memory read memory write MRM MRL Interrupt acknowledge special cycles I O read I O write Supported target functions...

Страница 2: ...l devices 0oC Tj 85oC Table 1 Core Implementation Supported Device Power Supply PCI32 66 Virtex XCV200 FG256 6C 3 3V only Virtex E XCV200E FG256 6C 3 3V only Virtex E XCV400E FG676 6C 3 3V only Virtex...

Страница 3: ...y applications that need a PCI interface General Description The Xilinx PCI interface is a pre implemented and fully tested module for Xilinx FPGAs The pinout for each device and the relative placemen...

Страница 4: ...lity and flexibility in PCI designs The Smart IP technol ogy is incorporated in every PCI interface Xilinx Smart IP technology leverages the Xilinx architectural advantages such as look up tables and...

Страница 5: ...bility including the ability to implement a capabilities pointer in configuration space allows the user to implement functions such as power management and message signaled interrupts in the user appl...

Страница 6: ...es its performance from its ability to support burst transfers The performance of any PCI application depends largely on the size of the burst transfer Buffers to support PCI burst transfer can effici...

Страница 7: ...locked into one DMA engine hence an optimized design that fits a specific application can be designed Recommended Design Experience The PCI Interface is pre implemented allowing engineering focus on...

Страница 8: ...s Timing Parameters in the 33 MHz Implementations Table 3 PCI Bus Commands CBE 3 0 Command PCI Initiator PCI Target 0000 Interrupt Acknowledge Yes Yes 0001 Special Cycle Yes Ignore 0010 I O Read Yes Y...

Страница 9: ...oat 40 Notes 1 Controlled by timespec constraints included in product 2 Controlled by SelectIO configured for PCI66_3 3 Controlled by guide file included in product Table 5 Timing Parameters 33 MHz Im...

Страница 10: ...tor system v7 1i or higher The Xilinx CORE Generator is bundled with the ISE Foundation v7 1i software at no additional charge To purchase the Xilinx PCI core please contact your local Xilinx sales re...

Страница 11: ...refix to device names 1 30 04 1 9 Updated to build v3 0 122 updated copyright information to 2004 4 9 04 1 10 Updated to build v3 0 126 updated Xilinx tools to 6 2i SP1 in supported devices table adde...

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