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PCI32 Interface v3.0

www.xilinx.com

DS206 August 31, 2005

Product Specification v3.0.151

Ordering Information

Build

v3.0.150

of the PCI core, with support added for Spartan-3E, is for available for download from the

Xilinx

IP Center

and can also be accessed through the Xilinx CORE Generator system v7.1i or higher.

The Xilinx CORE Generator is bundled with the ISE Foundation v7.1i software at no additional charge.
To purchase the Xilinx PCI core, please contact your local Xilinx

sales representative

Part Numbers

• DO-DI-PCI32-IP

- Access to the v3.0 PCI32 33 MHz Spartan and 66 MHz Virtex Families

• DX-DI-PCI32-SL

- Upgrade from PCI32 33 MHz Spartan only to v3.0 PCI32 33 MHz Spartan and 66 MHz Virtex

families

• DO-DI-PCI32-SP

- Access to the v3.0 PCI32 Spartan family project license

Содержание PCI32

Страница 1: ...dBus compliant Supported initiator functions Configuration read configuration write Memory read memory write MRM MRL Interrupt acknowledge special cycles I O read I O write Supported target functions...

Страница 2: ...l devices 0oC Tj 85oC Table 1 Core Implementation Supported Device Power Supply PCI32 66 Virtex XCV200 FG256 6C 3 3V only Virtex E XCV200E FG256 6C 3 3V only Virtex E XCV400E FG676 6C 3 3V only Virtex...

Страница 3: ...y applications that need a PCI interface General Description The Xilinx PCI interface is a pre implemented and fully tested module for Xilinx FPGAs The pinout for each device and the relative placemen...

Страница 4: ...lity and flexibility in PCI designs The Smart IP technol ogy is incorporated in every PCI interface Xilinx Smart IP technology leverages the Xilinx architectural advantages such as look up tables and...

Страница 5: ...bility including the ability to implement a capabilities pointer in configuration space allows the user to implement functions such as power management and message signaled interrupts in the user appl...

Страница 6: ...es its performance from its ability to support burst transfers The performance of any PCI application depends largely on the size of the burst transfer Buffers to support PCI burst transfer can effici...

Страница 7: ...locked into one DMA engine hence an optimized design that fits a specific application can be designed Recommended Design Experience The PCI Interface is pre implemented allowing engineering focus on...

Страница 8: ...s Timing Parameters in the 33 MHz Implementations Table 3 PCI Bus Commands CBE 3 0 Command PCI Initiator PCI Target 0000 Interrupt Acknowledge Yes Yes 0001 Special Cycle Yes Ignore 0010 I O Read Yes Y...

Страница 9: ...oat 40 Notes 1 Controlled by timespec constraints included in product 2 Controlled by SelectIO configured for PCI66_3 3 Controlled by guide file included in product Table 5 Timing Parameters 33 MHz Im...

Страница 10: ...tor system v7 1i or higher The Xilinx CORE Generator is bundled with the ISE Foundation v7 1i software at no additional charge To purchase the Xilinx PCI core please contact your local Xilinx sales re...

Страница 11: ...refix to device names 1 30 04 1 9 Updated to build v3 0 122 updated copyright information to 2004 4 9 04 1 10 Updated to build v3 0 126 updated Xilinx tools to 6 2i SP1 in supported devices table adde...

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