8
XAPP168 (v1.1) February 8, 2000
1-800-255-7778
Getting Started With the MultiLINX™ Cable
R
Boundary Scan Connection
Boundary Scan connections, shown in
, need only use the standard four JTAG leads:
•
TMS
•
TCK
•
TDI
•
TDO
However, reconfiguration requires access to the PROG pin.
•
PROG
Figure 5: SelectMAP With Capture
x168_05_091999
Xilinx Device
MultiLINX Connectors
Circuit Board
Note: Pull-up resistors are 4.7k ohm
VCC
M2
D7
D6
D5
D4
D3
D2
D1
D0
User I/O
User I/O:
TRIGGER
BUSY/DOUT
INIT
PROG
DONE
CCLK
GCK (x)
User I/O
Capture Control
Logic
User Logic
Filp-flops and Latches,
LUTRAMs,
and Block RAMs
PWR
GND
CCLK
DONE (D/P)
DIN
PROG
INIT
RST
RT
RD (TDO)
TRIG
TDI
TCK
TMS
CLK1-IN
CLK1-OUT
WRITE
VCC
M1
VCC
M0
CS
GCK (y)
System Clock (y)
CAPTURE
CAPCLK
D0
D1
D2
D3
D4
D5
D6
D7
CS0 (CS)
CS1
CS2
CLK2-IN
CLK2-OUT
WS
RS (RDWR)
RDY/BUSY
4
3
2
1