6
XAPP168 (v1.1) February 8, 2000
1-800-255-7778
Getting Started With the MultiLINX™ Cable
R
Note: Serial verification is not used with Virtex FPGAs.
SelectMAP Connection
The SelectMAP interface to Virtex FPGAs, shown in
, require the use of the following
leads:
•
PROG
•
CCLK
•
DONE
•
INIT
•
D0 - D7
•
RS (RDWR)
Figure 3: Serial Configuration and Verify
x168_03_091999
Xilinx Device
MultiLINX Connectors
VCC
Circuit Board
(Optional:
Only Used f
or Prob
ling)
Note: Pull-up resistors are 4.7k ohm
VCC
VCC
M2
TCK
User I/O: RESET
INIT
PROG
DIN
DONE
CCLK
User I/O:
R
T
User I/O:
RD
User I/O:
TRIGGER
PWR
GND
CCLK
DONE (D/P)
DIN
PROG
INIT
RST
RT
RD (TDO)
TRIG
TDI
TCK
TMS
CLK1-IN
CLK1-OUT
TMS
GCK (x)
System Clock (x)
GCK (y)
VCC
M1
VCC
M0
VCC
VCC
VCC VCC
D0
D1
D2
D3
D4
D5
D6
D7
CS0 (CS)
CS1
CS2
CLK2-IN
CLK2-OUT
WS
RS (RDWR)
RDY/BUSY
4
3
2
1
System Clock (y)