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ML40

x

 EDK Processor Reference Design

UG082 (v5.0) June 30, 2006

Chapter 8:

PLB TFT LCD Controller

R

 

Table 8-5:

Parameters

Name

Default Description 

C_DCR_BASEADDR 

N/A 

Base address of DCR control registers. 
Must be aligned on an even DCR 
address boundary (least significant bit 
= 0).

C_DCR_HIGHADDR 

N/A 

Upper address boundary, must be set to 
value of C_DCR_BA 1.

C_DEAFULT_TFT_BASE_ADDR[0:10] 

N/A 

Most significant bits of base address for 
video memory. The 11 most significant 
bits of this address define the 2 MB 
region of memory used for the video 
frame storage.

C_DPS_INIT 

1 

Initial reset state of DPS control bit: 

0 = DPS output bit resets to 0.
This initializes the display to use a 
normal scan direction.

1 = DPS output bit resets to 1.
This initializes the display to use a 
reverse scan direction (rotates screen 
180 degrees). 

C_ON_INIT 

1 

Initial reset state of TFT enable/disable 
bit:

0 = Disable TFT display on reset.
This causes a black screen to be 
displayed on reset.

1 = Enable TFT display on reset.
This causes the PLB TFT LCD 
controller to operate normally on 
reset. 

Содержание ML40 Series

Страница 1: ...R ML40x EDK Processor Reference Design User Guide for EDK 8 1 UG082 v5 0 June 30 2006...

Страница 2: ...PECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES THE TOTAL CUMU...

Страница 3: ...ng New Users 17 Documentation Provided by Xilinx 17 IBM CoreConnect Documentation 17 Chapter 2 ML40x Embedded Processor Reference System Introduction 19 Hardware 19 Overview 19 Processor Local Bus PLB...

Страница 4: ...e IV or Platform Cable USB iMPACT Program 37 Download Using the System ACE Interface 38 Software 39 Building the Linux BSP PPC405 Systems Only 41 Chapter 4 Introduction to Hardware Reference IP Introd...

Страница 5: ...0 June 30 2006 R Implementation 64 Memory Map 65 Chapter 8 PLB TFT LCD Controller Overview 71 Related Documents 71 Features 71 Module Port Interface 71 Hardware 75 Implementation 75 Video Timing 76 Me...

Страница 6: ...6 www xilinx com ML40x EDK Processor Reference Design UG082 v5 0 June 30 2006 R...

Страница 7: ...uction to Hardware Reference IP Chapter 5 Using IPIF to Build IP Figure 5 1 IPIF SRAM Module Interface 46 Figure 5 2 IPIF Simple SRAM Write Cycle 47 Figure 5 3 IPIF Simple SRAM Read Cycle 48 Figure 5...

Страница 8: ...8 www xilinx com ML40x EDK Processor Reference Design UG082 v5 0 June 30 2006 R...

Страница 9: ...1000 0x90001004 32 Table 2 8 Single Ended Expansion Header GPIO Regs Addr 0x90001008 0x9000100C 33 Chapter 3 EDK Tutorial and Demonstration Table 3 1 Demonstration Software Applications 39 Chapter 4 I...

Страница 10: ...ference Design UG082 v5 0 June 30 2006 R Table 8 2 PLB Master Signals 72 Table 8 3 DCR Slave Signals 73 Table 8 4 External Output Pins 73 Table 8 5 Parameters 74 Table 8 6 Pixel Color Encoding 78 Tabl...

Страница 11: ...Reference System Chapter 3 EDK Tutorial and Demonstration Chapter 4 Introduction to Hardware Reference IP Chapter 5 Using IPIF to Build IP Chapter 6 OPB AC97 Sound Controller Chapter 7 OPB PS 2 Contr...

Страница 12: ...trl C Italic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Development System Reference Guide for more information Emph...

Страница 13: ...mple Blue text Cross reference link to alocation in the current document See the section Additional Resources for details Refer to Title Formats in Chapter 1 for details Red text Cross reference link...

Страница 14: ...14 www xilinx com ML40x EDK Processor Reference Design UG082 v5 0 June 30 2006 Preface About This Guide R...

Страница 15: ...hardware and software The reference system is intended to familiarize users with the Virtex 4 product its design tool flows and its features It provides a foundation for those who are learning how to...

Страница 16: ...roBlaze or PowerPC processor Chapter 2 ML40x Embedded Processor Reference System and Chapter 3 EDK Tutorial and Demonstration have instructions on how to synthesize and run the designs through the Xil...

Страница 17: ...tion Provided by Xilinx Virtex 4 Data Sheet DC and Switching Characteristics http www xilinx com bvdocs publications ds302 pdf Virtex 4 User Guide http www xilinx com bvdocs userguides ug070 pdf IBM C...

Страница 18: ...18 www xilinx com ML40x EDK Processor Reference Design UG082 v5 0 June 30 2006 Chapter 1 Introduction to the ML40x Embedded Processor Reference System R...

Страница 19: ...cols and capabilities of the FPGA Hardware Overview Figure 2 1 page 20 provides a high level view of the hardware contents of the Embedded MicroBlaze Processor System Figure 2 2 page 21 provides an ov...

Страница 20: ...82_02_01_050406 DDR Memory USB Memory Mapped DCR Bus DDR MEMC OPB2PLB Bridge ZBT SRAM Flash Buttons LEDs IIC and misc I Os PLB ARB OPB ARB Ethernet IPIF UART EMC DCR Bridge IPIF MDM PS 2 PS 2 IPIF Sys...

Страница 21: ...USB Memory Mapped DCR Bus DDR MEMC PLB2OPB Bridge BRAM BRAM MEMC ZBT SRAM Flash PLB ARB OPB ARB Ethernet IPIF IIC UART EMC DCR Bridge IPIF IPIF PS 2 PS 2 System ACE MPU IPIF INTC IPIF IPIF EMC IPIF A...

Страница 22: ...he reference design includes a 64 bit PLB infrastructure with 64 bit master and slave devices attached The PLB devices in the reference system include PLB Masters 640x480 VGA Controller OPB to PLB Bri...

Страница 23: ...odules to further simplify IP development The IPIF converts the OPB protocol into common interfaces such as an SRAM protocol or a control register interface IPIF modules also provide support for DMA a...

Страница 24: ...pace The DCR slave devices connected to the OPB to DCR Bridge include PLB Arbiter if enabled VGA TFT LCD Controller The DCR specification requires that the DCR master and slave clocks be synchronous t...

Страница 25: ...other This synchronous phase alignment is required by the CPU and many other devices so they can pass signals from one clock domain to another After a system reset or at FPGA startup a debounce circui...

Страница 26: ...B error acknowledge condition PLB errors Error 2 LED on the ML40x board signal a PLB timeout or data error acknowledge condition as reported by the PLB arbiter Control registers in the design allow th...

Страница 27: ...C405 systems 1 01 d EDK Installation opb_intc 1 00 c EDK Installation opb_mdm MicroBlaze systems 2 01 a ML401 2 00 a ML402 ML403 Local pcores Directory 2 EDK Installation opb_ps2_dual_ref 1 00 a Local...

Страница 28: ...ernet 60003FFF 8 KB A9000000 PS 2 Dual A9001FFF 512 B CF000000 System ACE MPU CF0001FF TFT Control Regs 0x080 0x081 8 B TFT VGA Controller D0000207 D0000200 A6000000 AC97 Sound A60000FF 256 B 192 MB P...

Страница 29: ...Address 0x90000000 0x90000004 Bit s Description 0 LSB General Purpose LED 0 1 General Purpose LED 1 2 General Purpose LED 2 3 General Purpose LED 3 4 Center Directional LED 5 West Directional LED 6 S...

Страница 30: ...Mouse Clock Valid only when PS 2 GPIO is enabled see ML40x Control Register 2 Bit 7 Reading this bit reads the value from the external pin Writing this bit sets the value of the external pin if the co...

Страница 31: ...controlled by the OPB IIC Controller if instantiated in system mhs 7 IIC PS 2 Writing this bit to a 1 makes the PS 2 mouse keyboard pins controlled via GPIO registers Writing this bit to a 0 makes th...

Страница 32: ...GPIO Registers Address 0x90002000 0x90002004 Bit s Description 0 LSB Character LCD Pin DB4 1 Character LCD Pin DB5 2 Character LCD Pin DB6 3 Character LCD Pin DB7 4 Character LCD Pin RW 5 Character LC...

Страница 33: ...0100C Table 2 8 Single Ended Expansion Header GPIO Regs Addr 0x90001008 0x9000100C Bit Description Bit Description 0 J6 Pin 2 16 J6 Pin 34 1 J6 Pin 4 17 J6 Pin 36 2 J6 Pin 6 18 J6 Pin 38 3 J6 Pin 8 19...

Страница 34: ...s to the system Adding or Removing IP Cores To remove an IP core 1 Delete the instantiation for that piece of IP from the system mhs file or use the Add Edit Cores feature of the EDK GUI 2 Delete all...

Страница 35: ...r Invoking the EDK tools This tutorial section and those that follow have directory path names that are shown separated by the character as per the UNIX convention For Windows the should be used to se...

Страница 36: ...supports multiple user software applications To select which software application to compile follow the instructions below 1 Click the Applications tab on the left hand pane then scroll down and look...

Страница 37: ...L40x board and power on the board 2 Click Device Configuration Download Bitstream within XPS Note This loads a bitstream containing a bootloop program that effectively idles the processor not the soft...

Страница 38: ...od creates an ACE file that contains the bitstream and software that can be saved to the CompactFlash device and inserted into the ML40x board 1 Within XPS select Device Configuration Generate System...

Страница 39: ...Using C s studio library prints Hello world and echoes characters entered via standard input to standard output sw standalone hello hello_uart Using the EDK UART driver prints Hello world on the UART...

Страница 40: ...files from CompactFlash via System ACE interface sw standalone testfatfs usb_hpi_test Echoes characters typed on a USB keyboard to the LCD and serial port on the ML40x sw standalone usb_hpi_test usb_...

Страница 41: ...build the Linux kernel are available from MontaVista http www mvista com For further information about using Linux with EDK refer to Xilinx XAPP765 Getting Started with EDK and MontaVista Linux 5 Pat...

Страница 42: ...42 www xilinx com ML40x EDK Processor Reference Design UG082 v5 0 June 30 2006 Chapter 3 EDK Tutorial and Demonstration R...

Страница 43: ...y of the ML40x Reference System s EDK project directory In addition to describing the individual hardware IPs this document also introduces the concept of the IP InterFace IPIF modules These modules a...

Страница 44: ...ion about the source code format and resource utilization for these cores Many of the IP blocks are parameterizeable so their size might increase or decrease depending on how they are configured These...

Страница 45: ...ple timing relationships and very light protocols The IPIF is designed to be bus agnostic This allows the backend interface for the IP to remain the same while only the bus interface logic in the IPIF...

Страница 46: ...clock edges The IPIF takes the clock from the OPB or PLB bus interface and passes it to the IP causing the IP to use the same global clock as the bus it is connected to The SRAM interface protocol use...

Страница 47: ...ng of the transaction It then waits for the IP device to acknowledge completion of the write by sending back a single clock cycle High pulse on IP2Bus_WrAck During the entire transaction from Bus2IP_W...

Страница 48: ...assert retry on the bus side and terminate the transaction IP2Bus_Error asserted with IP2Bus_RdAck IP2Bus_WrAck will cause the IPIF to signal an error on the bus interface For slow IP devices an IP2B...

Страница 49: ...ster If the output enable for a given pin is deasserted the pin s driver is put in a high impedance state allowing an external device to drive the pin The CPU can sense the current value of any pin re...

Страница 50: ...to the IPIF SRAM module This particular IPIF module was actually designed to serve this very purpose To connect a legacy IP simply connect the address data chip enable clock reset and interrupt pins t...

Страница 51: ...t with simulation to gain experience with IPIF The IPIF used in the ML40x Embedded Processor Reference System currently supports only the SRAM module Additional IPIF modules are available through EDK...

Страница 52: ...52 www xilinx com ML40x EDK Processor Reference Design UG082 v5 0 June 30 2006 Chapter 5 Using IPIF to Build IP R...

Страница 53: ...ler module allows full access to all control and status registers in the AC97 chip and provides data buffering for stereo playback and recording Related Documents The following documents provide addit...

Страница 54: ...ct OPB_seqAddr Input OPB sequential address OPB_AC97_CONTROLLER_DBus 0 31 Output Slave data bus OPB_AC97_CONTROLLER_errAck Output Slave error acknowledge OPB_AC97_CONTROLLER_retry Output Slave bus cyc...

Страница 55: ...to Base Address 0xFF or higher Total memory space from C_BASEADDR to C_HIGHADDR must be power of 2 C_PLAYBACK 1 Playback Enable Set to 1 to allow playback Set to 0 to remove playback logic C_RECORD 1...

Страница 56: ...uld poll the playback FIFO full status bit and refill the FIFO when it is not full If the playback FIFO goes into an underrun condition FIFO is empty and Codec requests more data an error flag bit is...

Страница 57: ...e control registers in the Codec chip the write data and then the address to be accessed are written to two registers in the OPB AC97 controller This causes the write data to be serialized and sent to...

Страница 58: ...eady to receive commands or data This can occur during initial power on or immediately after reset 1 Codec ready to run 27 R Register Access Finish 0 AC97 Controller waiting for access to control stat...

Страница 59: ...ol Address Register 0 Perform a write to the address specified above The write data comes from the AC97 Control Data Write Register which should be set beforehand 1 Performs a read to the address abov...

Страница 60: ...60 www xilinx com ML40x EDK Processor Reference Design UG082 v5 0 June 30 2006 Chapter 6 OPB AC97 Sound Controller R...

Страница 61: ...mit or receive conditions This document assumes the user is already familiar with the PS 2 interface protocol Additional information about PS 2 ports and peripherals is widely available on the Interne...

Страница 62: ...write OPB_seqAddr Input OPB sequential address Sln_XferAck Output Slave transfer acknowledge Sln_Dbus 0 31 Output Slave data bus Sln_DBusEn Output Slave data bus enable Sln_errAck Output Slave error...

Страница 63: ...082 v5 0 June 30 2006 Module Port Interface R Table 7 3 Parameters Name Description C_BASEADDR 32 bit base address of PS 2 controller must be aligned to 8 KB boundary C_HIGHADDR Upper address boundary...

Страница 64: ...terrupt driven mode separate register bits for setting clearing and masking of individual interrupts are provided Because the PS 2 interface uses an open collector circuit for transmitting data the ou...

Страница 65: ...setting and clearing the Interrupt Status Register and Interrupt Mask Register faster The register definitions are shown in Table 7 5 page 66 this table spans several pages Note The second PS 2 Port...

Страница 66: ...sy This register can only be modified by PS 2 SIE hardware Software does not have direct write permission to change this field because this field is set by the state machine in the SIE Software can cl...

Страница 67: ...egister INTCLR 4 offset x14 4 INSTA 5 tx_ackf 5 R Interrupt Status Register TX acknowledge received This field is updated by the PS 2 Serial Interface when the SIE completes transmission of a data byt...

Страница 68: ...a 0 has no effect If software tries to read from INTCLR offset x14 the value of INTSTA offset x10 is returned Base Address 24 Offset x18 INTMSET 2 rx_full 2 R W Interrupt Mask Set Register RX data reg...

Страница 69: ...to this field clears INTM 4 Writing a 0 has no effect INTMCLR 5 rx_ack 5 R W Interrupt Mask Clear Register TX acknowledge received Writing a 1 to this field clears INTM 5 Writing a 0 has no effect IN...

Страница 70: ...70 www xilinx com ML40x EDK Processor Reference Design UG082 v5 0 June 30 2006 Chapter 7 OPB PS 2 Controller Dual R...

Страница 71: ...iguring the controller Related Documents The following documents provide additional information IBM CoreConnect 32 Bit Device Control Register Bus Architecture Specifications IBM CoreConnect 64 Bit Pr...

Страница 72: ...ta acknowledge PLB_pendPri 0 1 Input PLB pending request priority PLB_pendReq Input PLB pending bus request indicator PLB_reqPri 0 1 Input PLB current request priority Mn_abort Output Master abort bus...

Страница 73: ...t DCR Write Strobe DCR_Ack Output DCR Acknowledge DCR_DBusOut 0 31 Output DCR Data Bus Out Table 8 4 External Output Pins Name Direction Description TFT_LCD_HSYNC Output Horizontal Sync Negative Polar...

Страница 74: ...address for video memory The 11 most significant bits of this address define the 2 MB region of memory used for the video frame storage C_DPS_INIT 1 Initial reset state of DPS control bit 0 DPS outpu...

Страница 75: ...he video synchronization signals including back porch and front porch blanking See Video Timing page 76 for more information The PLB TFT LCD Controller allows for the PLB clock and TFT video clocks to...

Страница 76: ...from This allows frames of video to be drawn in other memory locations without being seen on the display The software can then change the video memory base address to display a different frame when i...

Страница 77: ...Display period is 480 h_syncs tv tvp Figure 8 5 Vertical Data UG082_08_05_050406 D 0 Y tvp 2 h_syncs tvb 31 h_syncs DE 640 TFT Clocks tvf 12 h_syncs tvp 1 D X Y D X 0 D X 479 1 2 3 tvb tvf 480H Fixed...

Страница 78: ...pace only the first 640 columns and 480 rows are displayed on the screen For a given row 0 to 479 and column 0 to 639 the pixel color information is encoded as shown in Table 8 6 Table 8 6 Pixel Color...

Страница 79: ...his address must be aligned on a 2 MB boundary i e only the upper 11 bits are writable and the remaining address bits are always 0 DCR Base Address 1 31 2 Undefined 1 RW DPS control bit 0 Set DPS outp...

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