PLB PCI Full Bridge (v1.00a)
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DS508 March 21, 2006
Product Specification
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• If a SERR occurs during a valid data phase on a burst transfer, the PLB PCI Bridge causes an IPIF
timeout and asserts the IPIF Master Read SERR interrupt. SERR error on data phase could occur on
the first PCI transaction or on a subsequent transaction due to an abnormal disconnect that allowed
automatic reissue of the PCI read command. Most of the data transferred prior to the SERR
assertion will be transferred. Terminating the data transfer to the PLB master depends on the
throttling done by the target device and PLB/PCI clock ratio. After the SERR error is transferred
across the time-domain boundary, an IPIF timeout is allowed to occur and the IPIF asserts
Slv_MErr. In all cases, the PLB Master Read SERR interrupt is asserted.
• If the PLB PCI Bridge performs a master abort due to no response from a target, a PLB IPIF time-out
occurs.
• If on either a single transfer or the first data phase of a burst transfer, a PCI retry from the PCI target
occurs, the PLB PCI Bridge will immediately retry the read request and continue retying the request
until the transfer completes.
• If during a single transfer the target disconnects with data, the transfer will be completed.
• If on a single transfer, a PERR error is detected, data is transferred and the PLB Master Read PERR
interrupt is asserted. The PERR status register bit is set as well.
• If the target disconnects on a burst transfer, either with or without data, the v3.0 core terminates the
PCI transaction. When the PCI2IPIF FIFO occupancy is below the predetermined level (i.e.,
C_TRIG_PCI_READ_OCC_LEVEL), another PCI transaction is attempted as long as the PLB
master request is active. If a retry is issued on a subsequent PCI transfer, and the PLB master is
requesting more data, an automatic retry is issued when the FIFO occupancy is below the
predetermined level.
• If a PERR error is detected on a burst transfer, the PLB PCI Bridge aborts the PCI transaction and
data transfer to the IPIF is stopped and an IPIF timeout is allowed to occur. When an IPIF timeout
occurs, Slv_MErr is asserted by the IPIF. The PLB Master Read PERR interrupt is asserted and the
PERR status register bit is set as well.
• If the initiator latency timer expires on a burst transfer, the PLB PCI Bridge terminates the PCI
transaction. When the PCI2IPIF FIFO occupancy is below the predetermined level, another PCI
transaction is attempted as long as the PLB master request is active.
• If a target abort occurs, data transfer to the IPIF is stopped and an IPIF timeout is allowed to occur.
In addition, the PLB Target Abort Master Read interrupt is asserted. When an IPIF timeout occurs,
Slv_MErr is asserted by the IPIF. Recall that a target abort indicates that the target cannot proceed
with subsequent transactions; this is expected to be a major failure most likely requiring a reset.
• If the address attempts to go beyond the valid range on a burst transfer, the PLB PCI Bridge
terminates the PCI read operation on the last valid address. The FIFO contains only data from valid
addresses and transfers to the IPIF continue until the PLB master terminates the transaction or the
FIFO is empty. Note that the PLB IPIF does not test for the case of the implied incrementing of the
PLB address incrementing beyond a valid range on a burst, hence, the request can continue when
the FIFO is empty. If this occurs, the bridge will allow an IPIF timeout to occur. When an IPIF
timeout occurs, Slv_MErr is asserted by the IPIF.
