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AXI Bridge for PCI Express v2.4
50
PG055 June 4, 2014
Chapter 3:
Designing with the Core
Clocking Interface
defines the clocking interface signals.
The Clocking architecture is described in detail in the Use Model chapter of the
7 Series
FPGAs GTX/GTH Transceivers User Guide (UG476)
.
AXI Transactions for PCIe
are the translation tables for AXI4-Stream and memory-mapped
transactions.
Table 3-2:
Clocking Interface Signals
Name
Direction
Description
pipe_pclk_in
Input
Parallel clock used to synchronize data transfers across the
parallel interface of the GTX transceiver.
pipe_rxusrclk_in
Input
Provides a clock for the internal RX PCS datapath.
pipe_rxoutclk_in
Input
Recommended clock output to the FPGA logic.
pipe_dclk_in
Input
Dynamic reconfiguration clock.
pipe_userclk1_in
Input
Optional user clock.
pipe_userclk2_in
Input
Optional user clock.
pipe_mmcm_lock_in
Input
Indicates if the MMCM is locked onto the source CLK.
pipe_txoutclk_out
Output
Recommended clock output to the FPGA logic.
pipe_rxoutclk_out
Output
Recommended clock output to the FPGA logic.
pipe_pclk_sel_out
Output
Parallel clock select.
pipe_gen3_out
Output
Indicates the PCI Express operating speed.
pipe_mmcm_rst_n
MMCM reset port. This port could be used by the upper layer to
reset MMCM if error recovery is required. If the system detects
the deassertion of MMCM lock, Xilinx recommends that you
reset the MMCM. The recommended approach is to reset the
MMCM after the MMCM input clock recovers (if MMCM reset
occurs before the input reference clock recovers, the MMCM
might never relock). After MMCM is reset, wait for MMCM to
lock and then reset the PIPE Wrapper as normally done.
Currently this port is tied High.
Table 3-3:
AXI4 Memory-Mapped Transactions to AXI4-Stream PCIe TLPs
AXI4 Memory-Mapped Transaction
AXI4-Stream PCIe TLPs
INCR Burst Read of 32-bit address AXIBAR
MemRd 32 (3DW)
INCR Burst Write to 32-bit address AXIBAR
MemWr 32 (3DW)