Figure 6: Sample Output from lstopo-no-graphics
In the above example, the even numbered CPU cores share an L3 cache, and the odd numbered
CPU cores share another L3 cache.
Alternatively, consult the documentation for your server and for its processor.
Determine and Set Interrupt Affinity for Queues
As well as the layout of your processor, you must determine the layout of interrupts for the
receive and transmit queues.
To determine and set interrupt affinity for the receive and transmit queues, use the following
commands:
• To view the interrupts assigned to a particular interface:
$ ls /sys/class/net/<interface>/device/msi_irqs/
For example to view the interrupts assigned to the enp1s0f0np0 interface:
$ ls /sys/class/net/enp1s0f0np0/device/msi_irqs/
46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
82 83 84 85 86 87 88 89 90 91 92 93
Chapter 5: Tuning
UG1523 (v1.0) October 18, 2022
Alveo X3522 User Guide
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