Xaoc Devices Drezno II Скачать руководство пользователя страница 6

6

                      01010111

 

              00111110

            00110101

          00101011

           00111001

                     01011100

                                     10000000

fig. 3: the principle of a/d conversion

(offset). To achieve a bipolar output signal, 
set the 
offset slider to a lower position, sub-
tracting some voltage from the positive-only 
output of the D/A converter and making it 
swing around 0V.

The D/A converter is calibrated and offers 
precise 1/12V steps when the 
gain slider is at 
maximum. A range of 256 semitones is equiv-
alent to over 20 octaves or over 20Vpp, which 
may sometimes be impractical. The 
dac range 
miniature switch 

12

 selects between this full 

range and a narrower 10+ octave range (128 
semitones)  by  ignoring  the  lowest  significant 
bit and scaling everything down by 1/2.

The illuminated link button 

13

 connects the 

data arriving at the Leibniz in header at the 
back as normalization signals for the 
bit in-
puts.
 Patching any cable into any DAC binary 

input breaks its normalization and overrides 
it with the external signal. However, with no 
signals patched to the inputs, the converter re-
ceives either the bits from the Leibniz data ca-
ble (when 
link is engaged) or just 00000000 
(when 
link is off). This arrangement allows 
you to replace only a few bits from the in-
coming data or disconnect the DAC from the 
Leibniz source entirely and use only the front 
panel jacks.

THE PRINCIPLE OF OPERATION

The ADC section of Drezno II converts analog 
signals to digital numbers. This process con-
sists of sampling the voltage at each clock 
cycle followed by quantization of the sampled 
value (fig. 3). During quantization, the value 
is compared to a set of discrete levels, which 
are numbered from 0 to 255. For example, if 

      10001111

               10010110

                   10101101

                 10011011

 10001010

10010011

Voltage

Code

Time

Time

the principle

of operation

quantizer

sample & 

hold

Input signal

Output data

ADC clock

Содержание Drezno II

Страница 1: ...DREZNO binary conversion komputor ii Model of 1989 operator s manual rev 1989 2 0...

Страница 2: ...semitone steps and 20Vpp 256 semitone steps To better understand the device and avoid common pitfalls we strongly advise the user to read through the entire manual before us ing the module INSTALLATI...

Страница 3: ...t digit bit is the least significant For example in an 8 bit system the highest bit represents 27 128 and the lowest bit represents 20 1 Since there are eight bits and each can have only two values th...

Страница 4: ...4 fig 2 drezno ii interface controls overview 1 8 4 10 3 5 11 13 7 2 6 9 12...

Страница 5: ...With gain set to max a 10Vpp input signal will fit the entire range while a hotter signal might need to be attenuated depending on the desired result The A D converter is clocked internally at a very...

Страница 6: ...ation signals for the bit in puts Patching any cable into any DAC binary input breaks its normalization and overrides it with the external signal However with no signals patched to the inputs the conv...

Страница 7: ...es through the Leibniz data ribbon cable It is possible to connect a chain of multiple Leibniz modules connected in series or even build a complex system with data splits and loops Feeding a time vary...

Страница 8: ...For example if there is an active 5V gate at input 7 and 0V at all the re maining inputs the code is 10000000 which means 128 in the decimal system This is the middle number of the 0 255 range of num...

Страница 9: ...ime about380ns Therefore the digital code resulting from this conversion is not instantly available For this reason Drezno II delays the clock s rising edge by about 450ns to account for conversion ti...

Страница 10: ...e range of 10V to 10V is exceeded When the switch is set to low the DAC section halves its output range and the least significant bit is ignored In other words a 1 12V step corresponds to the input bi...

Страница 11: ...dual binary outputs deliver pulse waveforms that flip between 0V and 5V many times per input period depending on the level of details they represent The average frequency of each individual input is t...

Страница 12: ...RIGINALLY ACQUIRED HOWEVER IN SPECIFIC CASES WE RESERVE THE RIGHT TO CHARGE FOR LABOR PARTS AND TRANSIT EXPENSES WHERE APPLICABLE RETURN POLICY THE DEVICE INTENDED FOR REPAIR OR REPLACEMENT UNDER WARR...

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