5
tation on the Leibniz header of each module
(not always pointing in the same direction).
Incorrectly plugged cables will result in en-
tirely erroneous operation.
warning: never plug power into the
10-pin leibniz data headers,
as this
would heavily damage your Drezno II and
jeopardize other modules connected to it.
The module should be fastened by mounting
the supplied screws before powering up.
MODULE OVERVIEW
Drezno II (fig. 2) consists of two sections that
can work independently or as a linked pair.
The adc input
1
accepts CV and audio sig-
nals. There are eight A/D bit outputs
2
,
representing each of the eight bits (7 down
to 0) with a 5V gate signal. In addition, bit
outputs' activity is indicated by the corre-
sponding set of eight yellow adc activity
map LEDs
3
.
The illuminated gain
4
and offset
5
slid-
ers allow you to adapt the range of the input
analog signal to the A/D converter's dynamic
range. The sliders' bi-color LEDs indicate sig-
nal amplitude (gain), clipping (offset), and
polarity (both). The colors are used accord-
ing to industrial standards: red represents
positive, and green represents negative val-
ues. The converter chip expects only positive
voltages, so for bipolar input signals, set the
offset slider in the upper position, which will
add some voltage to shift everything above 0V.
With gain set to max, a 10Vpp input signal
will fit the entire range, while a hotter signal
might need to be attenuated (depending on
the desired result).
The A/D converter is clocked internally at a
very high rate (near 2MHz), which helps to
avoid aliasing for audio rate signals, but it also
means the binary output signals may change
at extreme rates. The adc clock input
6
allows you to override the internal clock with
your own clock, which is necessary when you
want to slow down the rate both at the front
panel jacks and in the Leibniz data output. It
accepts gate, trigger, and clock signals, and re-
acts to the rising edge.
The DAC section mirrors the ADC section.
There are eight D/A bit inputs
7
, accept-
ing 5V gate signals representing each of the
bits numbered from 7 to 0. The dac output
8
produces a CV or audio signal based on the
input code. The dac clock input
9
expects
gate/trigger signals and is normalled to the
clock delivered via the ribbon cable connect-
ed to the Leibniz in data socket at the back of
the module. Therefore, even though the DAC
clock by default follows the ADC clock, it can
be replaced by a clock produced by any Leib-
niz module, and it can be overridden by any
signal patched through the panel socket.
The DAC section also features gain
10
and
offset
11
sliders which set the level and shift
of the dac output signal. Similarly, their
bi-color LEDs indicate the amplitude and po-
larity of the output signal (gain) and warn
against possible clipping at the output stage
