WM8804
Production Data
w
PD Rev 4.1 September 2007
24
REGISTER
ADDRESS
BIT LABEL DEFAULT
DESCRIPTION
R6
PLL4
06h
4 PRESCALE
0
PLL Pre-scale Divider Select
0 = Divide by 1 (PLL input clock =
oscillator clock)
1 = Divide by 2 (PLL input clock =
oscillator clock
÷
2)
R7
PLL5
07h
1:0 FREQMODE[1:0]
10
PLL Post-scale Divider Select
Selects the PLL output divider value
in conjunction with MCLKDIV and
CLKOUTDIV.
Refer to Table 23 for details of
FREQMODE operation.
Note: FREQMODE[1:0] bits are
automatically set in S/PDIF
Receive Mode.
Table 22 Pre and Post PLL Clock Divider Control
PLL CONFIGURATION EXAMPLE
Consider the situation where the oscillator clock (OSCCLK) input frequency is fixed at 12MHz and
the required MCLK frequency is 12.288MHz.
1. Calculate the f
2
, FREQMODE and MCLKDIV Values
The PLL is designed to operate with best performance when the f
2
clock is between 90 and 100MHz.
The necessary MCLK frequency is 12.288MHz. Choose MCLKDIV and FREQMODE values to set
the f
2
frequency in the range of 90 to 100MHz. In this case, the default values (MCLKDIV = 0 and
FREQMODE[1:0] = 10) will set the f
2
frequency at 98.304MHz; this value is within the 90 to 100MHz
range and is hence acceptable.
•
MCLKDIV
=
0
•
FREQMODE[1:0]
=
10
•
f
2
= 98.304MHz
2. Calculate R Value
Using the relationship: R = (f
2
÷ f
1
), the value of R can be calculated.
•
R
=
(f
2
÷ f
1
)
•
R = (98.304 ÷ 12)
•
R
=
8.192
3. Calculate PLL_N Value
The value of PLL_N is the integer (whole number) value of R, ignoring all digits to the right of the
decimal point. In this case, R is 8.192, hence PLL_N is 8.
4. Calculate PLL_K Value
The PLL_K value is simply the integer value of (2
22
(R-PLL_N)).
•
PLL_K = integer part of (2
22
x (8.192 – 8))
•
PLL_K = integer part of 805306.368
•
PLL_K = 805306 (decimal) / C49BA (hex)
A number of example configurations are shown in Table 23. Many other configurations are possible;
Table 23 shows only a small number of valid possibilities.
