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Intern
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stricted Confidential
User Manual
SPI_MISO
2nd_SPI master in slave out
I
SDC1/1st_SPI
SDC1_DATA_3
SDC1_DATA_3
I/O
1st_SPIM_MOSI
1st_SPI master out slave in
O
SDC1_DATA_2
SDC1_DATA_2
I/O
1st_SPIM_MISO
1st_SPI master in slave out
I
SDC1_DATA_1
SDC1_DATA_1
I/O
1st_SPIM_EN_1
1st_SPI chip select
O
SDC1_DATA_0
SDC1_DATA_0
I/O
1st_SPIM_CLK
1st_SPI serial clock
O
SDC1_CMD
SDC1_CMD
I/O
SDC1_CLK
SDC1_CLK
O
Module Control and
State Interfaces
WWAN_STATE
Wireless WAN Radio State
O
POWER_ON
Power On the module
I
WAKEUP_OUT
Module wakes up host OR GPIO O
WAKEUP_IN
Hostwakes upmodule OR GPIO. I
RESET
Reset the module
I
Power and Ground
VREF
Voltage Reference Output
O
VCC
Main Power
I
GND
GND
I
General Purpose
GPIO
Digital I/O
I/O
ADC_CONVENTOR
ADC_CONVENTOR
I
AUDIO
PCM/I2S
PCM_DIN
PCM_DIN
IO
AUX_BT_I2S_DATA0
AUX_BT_I2S_DATA0
IO
PCM_DOUT
PCM_DOUT
IO
AUX_BT_I2S_DATA1
AUX_BT_I2S_DATA1
IO
PCM_CLK
PCM_CLK
O
AUX_BT_I2S_SCK
AUX_BT_I2S_SCK
O
PCM_SYNC
PCM_SYNC
O
AUX_BT_I2S_WS
AUX_BT_I2S_WS
O
RFU
RFU
RFU
Reserved For Future Use
I
Debug
JTAG
MDM_JTAG_SRST_N
JTAG reset for debug
I
MDM_JTAG_TCK
JTAG clock input
I
MDM_JTAG_TDI
JTAG data input
I
MDM_JTAG_TDO
JTAG data output
O
MDM_JTAG_TMS
JTAG mode select input
I
MDM_JTAG_TRST_N
JTAG reset
O