Winbond W83627F, Руководство пользователя

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W83627HF/F
PRELIMINARY
Publication Release Date: November 2000
- 87 - Revision 1.0
7.5 HARDWARE GATEA20/KEYBOARD RESET CONTROL LOGIC
The KBC implements a hardware control logic to speed-up GATEA20 and KBRESET. This control logic
is controlled by LD5-CRF0 as follows:
7.5.1 KB Control Register (Logic Device 5, CR-F0)
BIT 7 6 5 4 3 2 1 0
NAME
KCLKS1 KCLKS0 Reserved Reserved Reserved P92EN HGA20 HKBRST
KCLKS1, KCLKS0
This 2 bits are for the KBC clock rate selection.
= 0 0 KBC clock input is 6 Mhz
= 0 1 KBC clock input is 8 Mhz
= 1 0 KBC clock input is 12 Mhz
= 1 1 KBC clock input is 16 Mhz
P92EN
(Port 92 Enable)
A "1" on this bit enables Port 92 to control GATEA20 and KBRESET.
A "0" on this bit disables Port 92 functions.
HGA20
(Hardware GATE A20)
A "1" on this bit selects hardware GATEA20 control logic to control GATE A20 signal.
A "0" on this bit disables hardware GATEA20 control logic function.
HKBRST
(Hardware Keyboard Reset)
A "1" on this bit selects hardware KB RESET control logic to control KBRESET signal.
A "0" on this bit disable hardware KB RESET control logic function.
When the KBC receives a data follows a "D1" command, the hardware control logic sets or clears GATE
A20 according to the received data bit 1. Similarly, the hardware control logic sets or clears KBRESET
depending on the received data bit 0. When the KBC receives a "FE" command, the KBRESET is pulse
low for 6
µ
S(Min.) with 14
µ
S(Min.) delay.
GATEA20 and KBRESET are controlled by either the software control or the hardware control logic and
they are mutually exclusive. Then, GATEA20 and KBRESET are merged along with Port92 when
P92EN bit is set.
7.5.2 Port 92 Control Register (Default Value = 0x24)
BIT
7 6 5 4 3 2 1 0
NAME Res. (0) Res. (0) Res. (1) Res. (0) Res. (0) Res. (1) SGA20 PLKBRST
SGA20
(Special GATE A20 Control)
A "1" on this bit drives GATE A20 signal to high.
A "0" on this bit drives GATE A20 signal to low.
PLKBRST
(Pull-Low KBRESET)
A "1" on this bit causes KBRESET to drive low for 6
µ
S(Min.) with 14
µ
S(Min.) delay. Before issuing
another keyboard reset command, the bit must be cleared.