GR64 Integrators Manual
Page: 34/104
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5.3.1
Level Translator Interfaces
Two different level translator circuits are implemented in GR64. The ‘common’
interface is used on all level-translated IO with the exception of the I2C signals, SDA
& SCL.
5.3.1.1
Common Level Translator Interface
The common level translator used within the GR64 uses a Maxim MAX3001E. The
level translators have built-in ESD protection to ±15kV (HBM).
Figure 8: Common level translator circuitry using MAX3001
VREF represents the application side while VL represents the Wireless CPU side.
Table 4: Level Translator I/O Logic Levels
Parameter
Min
Nom
Max
Unit
IO input voltage high threshold (V
IHC
)
0.75*VREF
VREF
V
IO input voltage low threshold (V
ILC
)
0
0.3
V
IO output voltage high threshold (V
OHC
)
0.67*VREF
VREF
V
IO output voltage low threshold (V
OLC
)
0
0.4
V
Rise and Fall time (C
L
= 15pF)
15
ns
IO input impedance (pulled to VREF or GND)
6
kohm
