VXIS VX1828B, Техническое описание

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VX1828B
Preliminary Datasheet Video Processor for Middle Size LCD Panel
P.31/P.64
V1.0 050420
6.2.2 ANALOG-FRONT-END REGISTERS
Bit Map Addr.
(Hex)
Name
Def.
(Hex)
7 6 5 4 3 2 1 0
06 AFE0 28 -
AFE_SYNC
_EN
VT VB CLAMP_MODE
07 AFE1 CA
STARTUP
_EN
PUMP_EN VCLAMPW CPW_LVL CPS_LVL
09 AFE3 88
VCLAMP_
EN
- VINI CMPLVL
0A AFE4 40 AFE_OFFSET
0B AFE5 80 PUPW
0C AFE6 40 PDNW
AFE_SYNC_EN 0 Analog synchronization reference OFF (df.)
1 Analog synchronization reference ON
[VT,VB] Combined together to provide 16 level of sync tip detection.
Normally distributed between 0 ~ 1.5V
CLAMP_MODE 00 Search-&-lock clamp mode
The sync tip level of active Y-channel is determined by the
AFE_OFFSET. Clamping of Y-channel is set by charge pump;
clamping of C-channel is set by voltage driver. The unused
channel is fixed at voltage level specified by VINI[1:0]. (df.)
10 Enhanced clamp mode
The sync tip level of active Y-channel is clamped at the
internal fixed value, which reduces the acquisition time
introduced by AFE_OFFSET. The active C-channel is
clamped by voltage driver. The unused channel is fixed at
voltage level specified by VINI[1:0].
11 Steady clamp mode
The sync tip level of all channels, active or unused, are
clamped at the internal fixed value, except the active
C-channel is clamped by voltage driver.
STARTUP_EN START-UP charge-pump control enable (df. = ON)
PUMP_EN Charge-pump control enable (df. = ON)
VCLAMPW Voltage clamp circuit activation control
0 20 active cycles (df.)
1 40 active cycles
2 60 active cycles
3 80 active cycles
CPW_LVL Strength adjustment of weak charge pump. It is used for fine