96
C
VMICPCI-7611 Product Manual
Device Interrupt Definition
PC/AT Interrupt Definition
The interrupt hardware implementation on the VMICPCI-7611 is standard for
computers built around the PC/AT architecture. The PC/AT evolved from the IBM
PC/XT architecture. In the IBM PC/XT systems, only eight Interrupt Request (IRQ)
lines exist, numbered from IRQ0 to IRQ7. These interrupt lines were included
originally on a 8259A Priority Interrupt Controller (PIC) chip.
The IBM PC/AT computer added eight more IRQx lines, numbered IRQ8 to IRQ15,
by cascading a second slave 8259A PIC into the original master 8259A PIC. The
interrupt line IRQ2 at the master PIC was committed as the cascade input from the
slave PIC. This master/slave architecture, the standard PC/AT interrupt mapping, is
illustrated in Figure C-2 on page 97 within the PCI-to-ISA Bridge PIIX4E 82371EB
section of the diagram.
To maintain backward compatibility with PC/XT systems, IBM chose to use the new
IRQ9 input on the slave PIC to operate as the old IRQ2 interrupt line on the PC/XT
Expansion Bus. Thus, in AT systems, the IRQ9 interrupt line connects to the old IRQ2
pin on the AT Expansion Bus (or ISA bus).
The BIOS defines the PC/AT interrupt line to be used by each device. The BIOS writes
to each of the two cascaded 8259A PIC chips an 8-bit vector, which maps each IRQx to
its corresponding interrupt vector in memory.
ISA Device Interrupt Map
The VMICPCI-7611 BIOS maps the IRQx lines to the appropriate device per the
standard ISA architecture. Reference Figure C-2 on page 97. This initialization
operation cannot be changed; however, a custom application could reroute the
interrupt configuration after the BIOS has completed the initial configuration cycle.
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com