Vizio VW42L HDTV10A, Руководство по обслуживанию

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CONFIDENTIAL – DO NOT COPY Page 7-34
File No. SG-0211
The DQ and DQS outputs are in the High-Z state, where they remain until driven in
normal operation (by a read access). After all power supply and reference voltages are
stable, and the clock is stable, the DDR SDRAM requires a 200µs delay prior to
applying an executable command.
Once the 200µs delay has been satisfied, a Deselect or NOP command should be
applied, and CKE must be brought HIGH. Following the NOP command, a Precharge
ALL command must be applied. Next a Mode Register Set command must be issued
for the Extended Mode Register, to enable the DLL, then a Mode Register Set
command must be issued for the Mode Register, to reset the DLL, and to program the
operating parameters. 200 clock cycles are required between the DLL reset and any
read command. A Precharge ALL command should be applied, placing the device in
the “all banks idle” state Once in the idle state, two auto refresh cycles must be
performed. Additionally, a Mode Register Set command for the Mode Register, with the
reset DLL bit deactivated (i.e. to program operating parameters without resetting the
DLL) must be performed.
Following these cycles, the DDR SDRAM is ready for normal operation.
DDR SDRAM’s may be reinitialized at any time during normal operation by asserting a
valid MRS command to either the base or extended mode registers without affecting
the contents of the memory array. The contents of either the mode register or extended
mode register can be modified at any valid time during device operation without
affecting the state of the internal address refresh counters used for device refresh.