Viglen VIG615M, Руководство пользователя

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V1.0 VIG615M Motherboard Manual
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Advance DRAM Configuration -> tRCD
When the DRAM Timing Mode sets to [Manual], the field is adjustable. When
DRAM is refreshed, both rows and columns are addressed separately. This setup
item allows you to determine the timing of the transition from RAS (row address
strobe) to CAS (column address strobe). The less the clock cycles, the faster the
DRAM performance.
Advance DRAM Configuration -> tRP
When the DRAM Timing Mode sets to [Manual], this field is adjustable. This setting
controls the number of cycles for Row Address Strobe (RAS) to be allowed to
precharge. If insufficient time is allowed for the RAS to accumulate its charge before
DRAM refresh, refresh may be incomplete and DRAM may fail to retain data. This
item applies only when synchronous DRAM is installed in the system.
Advance DRAM Configuration -> tRAS
When the DRAM Timing Mode sets to [Manual], this setting determines the time
RAS takes to read from and write to a memory cell.
Advance DRAM Configuration -> tRTP
When the DRAM Timing Mode sets to [Manual], this setting controls the time
interval between a read and a precharge command.
Advance DRAM Configuration -> tRC
When the DRAM Timing Mode sets to [Manual], the field is adjustable. The row
cycle time determines the minimum number of clock cycles a memory row takes to
complete a full cycle, from row activation up to the precharging of the active row.
Advance DRAM Configuration -> tWR
When the DRAM Timing Mode sets to [Manual], the field is adjustable. It specifies
the amount of delay (in clock cycles) that must elapse after the completion of a valid
write operation, before an active bank can be precharged. This delay is required to
guarantee that data in the write buffers can be written to the memory cells before
precharge occurs.
Advance DRAM Configuration -> tRRD
When the DRAM Timing Mode sets to [Manual], the field is adjustable. Specifies the
active-to-active delay of different banks.
Advance DRAM Configuration -> tWTR
When the DRAM Timing Mode sets to [Manual], the field is adjustable. This item
controls the Write Data In to Read Command Delay memory timing. This constitutes
the minimum number of clock cycles that must occur between the last valid write
operation and the next read command to the same internal bank of the DDR device.
Power User Mode
Press <Enter> to enter the sub-menu.

ADJUST CHANNEL 0/1 DRIVE
These two Groups are used to program RCOMP buffer strengths and slew
rate table for the various signal groups of MCH. Each channel contains seven
groups of signal (GROUP 0 ~ GROUP 6)