VIA Technologies VT82C686A, Руководство пользователя

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3: BIOS Setup Utility
PCI Dynamic
Bursting When enabled, every write transaction goes to the
write buffer. “Burstable” transactions then burst
on the PCI bus and “nonburstable” transactions do
not.
PCI Master 0 WS
Write
When enabled, writes to the PCI bus are executed
with zero wait states.
PCI Delay
Transaction The chipset has an embedded 32-bit posted write
buffer to support delay transactions cycles. Enable
to support compliance with PCI specification
version 2.1.
PCI#2 Access #1
Retry When enabled, the AGP Bus (PCI#1) access to
PCI Bus (PCI#2) is executed with the error retry
feature.
AGP Master 1 WS
Write This implements a single delay when writing to the
AGP Bus. By default, two-wait states are used by
the system, allowing for greater stability.
AGP Master 1 WS
Read This implements a single delay when reading to
the AGP Bus. By default, two-wait states are used
by the system, allowing for greater stability.
P6 Lock Function The P6 CPU has a PCI LOCK function to lock the
PCI BUS, enabling efficient sharing of the PCI
BUS with the PCI DEVICE and CPU.
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