VIA Technologies VT82C686A, Руководство пользователя

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3: BIOS Setup Utility
Advanced Chipset Features Page
This page sets some of the parameters of the mainboard
components including the memory, and the system logic.
CMOS Setup Utility – Copyright (C) 1984 – 2000 Award Software
Advanced Chipset Features
Bank 0/1 DRAM Timing SDRAM 8/10ns
Bank 2/3 DRAM Timing SDRAM 8/10ns
SDRAM Cycle Length 3
DRAM Clock Host CLK
Memory Hole Disabled
P2C/C2P Concurrency Enabled
Fast R-W Turn Around Disabled
System BIOS Cacheable Enabled
Video RAM Cacheable Enabled
OnChip AGP VGA Enabled
Frame Buffer Size 8M
AGP Aperture Size 64M
AGP-4X Mode Enabled
AGP Driving Control Auto
xAGP Driving Value DA
OnChip USB Enabled
USB Keyboard Support Disabled
OnChip Sound Auto
Item Help
Menu Level
   
: Move Enter : Select +/-/PU/PD:Value: F10: Save ESC: Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
Bank 0/1 2/3
DRAM Timing This item allows you to select the timing for the
DRAM slots, depending on whether the board has
paged SDRAMs.
SDRAM Cycle
Length This field enables you to set the CAS latency time
in HCLKs of 2/2 or 3/3. The system board
designer should have set the values in this field,
depending on the DRAM installed. Do not change
the values in this field unless you change
specifications of the installed DRAM or the
installed CPU.
DRAM Clock Enables the user to select the DRAM Clock.
Memory Hole
This item can be used to reserve memory space
for some ISA expansion cards that require it.
P2C/C2P
Concurrency When disabled, the CPU bus is occupied during
the entire PCI operation period.
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