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• S/PDIF output supports PCM, Dolby Digital, DTS digital audio transmission (32-48kHz Fs) using IEC 60958
and IEC 61937.
• Programmable I
2
S interface for connection to low-cost audio DACs.
• Integrated HDCP decryption engine for receiving protected audio and video content
• Pre-programmed HDCP keys provide highest level of key security, simplifies manufacturing
• Programmable registers via slave I
2
C interface
• 3.3V operation in 100-pin TQFP package
• Flexible power management
15.21. SN74CB3Q3305
15.21.1.
General Description
The SN74CB3Q3305 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of
the pass transistor, providing a low and flat ON-state resistance (r
on
). The low and flat ON-state resistance
allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The
device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data
bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q3305 provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
15.21.2.
Features
• High-Bandwidth Data Path (Up To 500 MHz)
• 5-V Tolerant I/Os with Device Powered-Up or Powered-Down
• Low and Flat ON-State Resistance (r
on
) Characteristics Over Operating Range (r
on
= 3
Ω
Typical)
• Rail-to-Rail Switching on Data I/O Ports
−
0- to 5-V Switching With 3.3-V VCC
−
0- to 3.3-V Switching With 2.5-V VCC
• Bidirectional Data Flow, With Near-Zero Propagation Delay
• Low Input/Output Capacitance Minimizes Loading and Signal Distortion (C
io(OFF)
= 3.5 pF Typical)
• Fast Switching Frequency (f
OE
= 20 MHz Max)
• Data and Control Inputs Provide Undershoot Clamp Diodes
• Low Power Consumption (ICC = 0.25 mA Typical)
• VCC Operating Range From 2.3 V to 3.6 V
• Data I/Os Support 0 to 5-V Signaling Levels (0.8-V, 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, 5-V)
• Control Inputs Can be Driven by TTL or 5-V/3.3-V CMOS Outputs
• I
off
Supports Partial-Power-Down Mode Operation
• Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II
• ESD Performance Tested Per JESD 22
−
2000-V Human-Body Model (A114-B, Class II)
−
1000-V Charged-Device Model (C101)
• Supports Both Digital and Analog Applications: USB Interface, Differential Signal Interface, Bus Isolation, Low-
Distortion Signal Gating
15.21.3.
Pin Connections
15.22. ST24LC21
15.22.1.
Description
The ST24LC21 is a 1K bit electrically erasable programmable memory (EEPROM), organized by 8 bits. This
device can operate in two modes: Transmit Only mode and I
2
C bidirectional mode. When powered, the device is
in Transmit Only mode with EEPROM data clocked out from the rising edge of the signal applied on VCLK. The
device will switch to the I
2
C bidirectional mode upon the falling edge of the signal applied on SCL pin. The
Содержание 17MB15E-5
Страница 1: ...i 42 PLASMA TV 17MB15E 5 SERVICE MANUAL ...
Страница 38: ...33 15 27 3 Pinning ...
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Страница 62: ...57 18 APPENDIX A 18 1 EXPLODED VIEW AND PART LIST ...
Страница 64: ...59 19 2 16 ELECTRICALDIAGRAMS 19 2 1 POWER BOARD ...
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Страница 80: ...73 19 4 PRINT_LAY OUTS 19 4 1 Complete_PCB_Pattern_Schematic ...
Страница 81: ...74 19 4 3 In 1_Ground_Level_PCB_Pattern ...
Страница 82: ...75 19 4 4 In2_Power_Level_PCB_Patter ...
Страница 83: ...76 19 4 5 Bottom_ Level_ PCB_ Pattern ...
Страница 84: ...77 19 4 6 Top_Layer_Silk_Print ...
Страница 85: ...78 19 4 7 Bottom_Layer_Silk_Print ...
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Страница 88: ...81 19 4 10 17fav15 2pcb ...
Страница 89: ...82 19 4 11 18amp05 2 pcb ...