Vertilon SIB164B, Руководство пользователя

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User Guide
- 9 -
Vertilon Corporation, 66 Tadmuck Road, Westford, MA 01886
/
Tel: (978) 692-7070
/
Fax: (978) 692-7010
/
www.vertilon.com
Specifications
(V
supply
= +5.0V, T
A
= +25C, unless otherwise noted)
Description Sym Min Typ Max Units Notes
HIGH VOLTAGE
High Voltage Input Load Resistance 50 M

Measured at high voltage input connector, J3.
HVMON to High Voltage Input Ratio 0.0015
± 5%
ANODE CIRCUITS
Quantity P1 - P64 64
Input Resistance R 2.2 M

Input Bias Voltage VB +0.250 V
Detector bias voltage supplied from PhotoniQ data
acquisition system.
LAST DYNODE PREAMPLIFIER
Input Coupling Capacitance C
in
0.1 uF
Input Resistance R
in
50

Input Parallel Resistance R
p
500

Amplifier #1 Gain A1 +3 +10 dB
V
in
is a triangular pulse (18 nsec rise time, 30 nsec fall time)
applied to last dynode preamplifier input (DY12).
Amplifier #2 Inverting Gain A2 0 dB
Amplifier #2 Output Impedance 50

Measured at preamplifier output, J5
LEADING EDGE DISCRIMINATOR
Threshold to Output Delay (V
in
=100mV) t
d1
10 nsec
V
in
is a triangular pulse (18 nsec rise time, 30 nsec fall time)
applied to last dynode preamplifier input (DY12).
Jitter (V
in
: 100mV) 500 psec
ZERO SLOPE DISCRIMINATOR
Amplifier #4 Inverting Gain A4 +20 dB
Threshold to Output Delay (V
in
=100mV) t
d3
35 nsec
V
in
is a triangular pulse (18 nsec rise time, 30 nsec fall time)
applied to last dynode preamplifier input (DY12). Gain set to
high, pulse width set to medium wide, threshold set to 10%.
Time Walk (V
in
: 10mV to 80mV) -5 nsec
Jitter (V
in
: 80mV) 1 nsec