Interfaces and Connectors
VL-MPEe-V5 Reference Manual
7
LVDS
F
LAT
P
ANEL
D
ISPLAY
C
ONNECTOR
The LVDS connector at location J2 is a 20-pin vertical Hirose-style connector.
The flat panel interface can support 18 or 24 bits of RGB pixel data plus three bits of
timing control (HSYNC/VSYNC/DE) on the four differential data output pairs. The LVDS
interface supports a maximum resolution of 1280 x 1024.
Table 4: LVDS Flat Panel Display Pinout
J2 Pin
Signal Name
Function
1
GND
Ground
2
NC
Not Connected
3
LVDSA3
Differential Data 3 (+)
4
LVDSA3#
Differential Data 3 (
-
)
5
GND
Ground
6
LVDSCLK0
Differential Clock (+)
7
LVDSCLK0#
Differential Clock (
-
)
8
GND
Ground
9
LVDSA2
Differential Data 2 (+)
10
LVDSA2#
Differential Data 2 (
-
)
11
GND
Ground
12
LVDSA1
Differential Data 1 (+)
13
LVDSA1#
Differential Data 1 (
-
)
14
GND
Ground
15
LVDSA0
Differential Data 0 (+)
16
LVDSA0#
Differential Data 0 (
-
)
17
GND
Ground
18
GND
Ground
19
+3.3V
+3.3V (Protected)
20
+3.3V
+3.3V (Protected)
The +3.3V power provided to pins 19 and 20 of J2 is protected by a software-
controllable power switch (1 A, maximum.). This switch is controlled by the FP_VDDEN
signal from the flat panel interface in the video controller.
