VersaLogic VL-586-1, Справочное руководство

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Hardware Jumper Summary
VL-586-1 Reference Manual Configuration – 21
Table 3: Jumper Summary (Cont.)
Jumper
Block
Description
As
Shipped Page
V18[1-2] CPU response to SYSRESET*
In — CPU resets whenever STD Bus SYSRESET* (P47) goes low
Out — CPU ignores activity on STD Bus SYSRESET* (P47)
Out 30
V18[3-4] Push-button Reset / Bus Interconnect
In — Connects STD Bus PBRESET* (P48) to CPU reset circuits
Out — CPU ignores activity on, and does not drive STD Bus PBRESET* (P48)
In 30
V18[5-6] Non-Maskable Interrupt / BUS Interconnect
In — Connects STD Bus NMIRQ* (P46) to CPU NMI input
Out — CPU ignores activity on STD Bus NMIRQ* (P46)
Out 30
V18[7-8] Permanent / Temporary Master Selection
In — Permanent Master Mode (V18[1-2] must be out, RP15 – RP22 must be in)
Out — Temporary Master Mode (RP15 – RP22 must be out)
In 30
V19[1-2] General Purpose Digital Input
In — Causes bit D5 (GP0) of the SCR register to read as “1”
Out — Causes bit D5 (GP0) of the SCR register to read as “0”
Out 30
V19[3-4] Multiprocessor Configuration
In — Dual master mode. Uses BUSAK* (P41) for bus arbitration.
Out — Permanent or temporary master mode.
Out 30
V19[5-6] Multiprocessor Configuration
In — Dual master mode. Uses BUSRQ* (P42) for bus arbitration.
Out — Permanent or temporary master mode.
Out 30