Special Registers
VL-EPICs-36 Reference Manual
49
Revision Level Register
REVLEV (Read Only) CA1h (or C91h)
D7
D6
D5
D4
D3
D2
D1
D0
RL4
RL3
RL2
RL1
RL0
EXT
CUST
BETA
Table 26: Revision Level Register Bit Assignments
Bit
Mnemonic
Description
D7-D3
RL
FPGA Revision Level
— These bits are hard-coded to represent the FPGA
revision. Contact VersaLogic Support for further information.
These bits are read-only.
D2
EXT
Extended Temperature
— Indicates operating temperature range.
0 = Standard temperature range
1 = Extended temperature range
This bit is read-only.
D1
CUSTOM
Custom Flag –
Indicates whether this is a custom FPGA.
0 = Standard
1 = Custom
This bit is read-only.
D0
REV
Beta Flag
— Indicates whether this is a Beta product.
0 = Standard
1 = Beta
This bit is read-only.