VL-EPICs-36 Reference Manual
26
Interfaces and Connectors
Video Output (J1 SVGA, J20 LVDS)
An on-board video controller integrated into the chipset provides high performance video output
for the VL-EPICs-36. The controller supports dual, simultaneous, independent video output.
C
ONFIGURATION
The video interface uses PCI interrupt INTA#. CMOS Setup is used to select the IRQ line routed
to INTA#.
The VL-EPICs-36 uses shared memory architecture. This allows the video controller to use
variable amounts of system DRAM for video RAM, up to 512 MB. The amount of RAM used for
video is set with a CMOS Setup option.
The VL-EPICs-36 supports two types of video output, SVGA and LVDS flat panel display,
which can be output simultaneously.
SVGA
O
UTPUT
C
ONNECTOR
(J1)
Adapter cable VL-CBR-1201 is available to translate the J1 connector into a standard 15-pin D-
Sub SVGA connector. This connector uses IEC 61000-4-2-rated TVS components to help protect
against ESD damage.
Table 5: Video Output Pinout
J1
Pin
Signal
Name
Function
Mini DB15
Pin
1
GND
Ground
6
2
RED
Red video
1
3
GND
Ground
7
4
GREEN
Green video
2
5
GND
Ground
8
6
BLU
Blue video
3
7
GND
Ground
5
8
HSYNC
Horizontal sync
13
9
GND
Ground
10
10
VSYNC
Vertical sync
14
11
CRT_SCL
DDC data clock line
15
12
CRT_SDA
DDC serial data line
12
5
5
