Interfaces and Connectors
VL-EPIC-25 Reference Manual
49
Analog Output
The Iguana uses a 12-bit Linear Technology LTC2634 D/A converter with four (4) single-ended
output signals. The converter has 5 µs per-channel update rate with a 0 to 4.096V output voltage
range.
The Iguana D/A converter is controlled using the SPI registers. The D/A converter is accessed
via SPI slave select 7 (writing 7h to the SS field in SPICONTROL). See "SPI Registers" for a
complete description of the registers.
See the
Linear Technology LTC2634 D/A Converter Datasheet
for programming information.
Table 19: Analog Output Pinout
J25
Pin
Signal
VL-CBR-4004
Connector
VL-CBR-4004
Pin (Label)
11
Analog Output 1
J3
5 (IO9)
12
Analog Output 2
Analog Output
4 (IO10)
13
Analog Output 3
3 (IO11)
14
Analog Output 4
2 (IO12)
15
Ground
1 (GND2)
Analog Output Using the SPI Interface
The following procedure can be used to set an analog output using the SPI interface.
1.
Write 27h to the SPICONTROL register (I/O address CA8h) – This value configures the
SPI port to select the D/A converter, 24-bit frame length, low SCLK idle state, rising
edge SCLK edge, and automatic slave select.
2.
Write 30h to the SPISTATUS register (I/O address CA9h) – This value selects 8 MHz
SCLK speed, hardware IRQ disable, and left-shift data.
3.
Write the LS 4-bits of the 12-bit output value into the MS 4-bits of SPIDATA1 (I/O
address CABh). For example, if writing a 12-bit value of 123h the value of 30h is written
to SPIDATA1.
4.
Write the MS 8-bits of the 12-bit output value to SPIDATA2 (I/O address CACh). For
example, if writing a 12-bit value of 123h the value of 12h is written to SPIDATA2.
5.
Write the analog output channel number (0 to 3) to Bits 3-0 and the write-and-update-
channel command 3h to Bits 7-4 of SPIDATA3 (I/O address CADh) – Any write
operation to this register triggers an SPI transaction. For example, if writing to the third
DAC channel (channel number 2) the value written to SPIDATA3 is 32h.
6.
Poll the SPI BUSY bit in the SPISTATUS register until the conversion is completed.
7.
The D/A output will be stable in no more than 5 µs.
