Interfaces and Connectors
EPM-14 Reference Manual
32
Video Interface
An on-board video controller integrated into the chipset provides high performance video output
for the EPM-14.
C
ONFIGURATION
The video interface uses PCI interrupt INTA*. CMOS Setup is used to select the IRQ line routed
to INTA*.
The EPM-14 uses shared memory architecture. This allows the video controller to use variable
amounts of system DRAM for video RAM. The amount of RAM used for video is set with a
CMOS Setup option.
The EPM-14 supports two types of video output, SVGA and LVDS Flat Panel Display. A CMOS
Setup option is used to select which output is enabled after POST.
V
IDEO
BIOS
S
ELECTION
Jumper V2[5-6] can be removed to allow the system to boot from the secondary video BIOS.
Unlike the primary video BIOS, the secondary video BIOS can be reprogrammed in the field.
SVGA
O
UTPUT
C
ONNECTOR
See the diagram
on page 15 for the location of connector J4. An adapter cable, part number CBR-
1201, is available to translate J4 into a standard 15-pin D-Sub SVGA connector.
This connector uses IEC 61000-4-2-rated TVS components to help protect against ESD damage.
Table 12: Video Output Pinout
J4
Pin
Signal
Name
Function
Mini DB15
Pin
1 GND
Ground
6
2 RED
Red
video
1
3 GND
Ground
7
4 GREEN Green
video
2
5 GND
Ground
8
6 BLUE
Blue
video
3
7 GND
Ground
5
8 HSYNC Horizontal
sync
13
9 GND
Ground
10
10 VSYNC
Vertical
sync
14
11
CRT_SCL
DDC data clock line
15
12
CRT_SDA
DDC serial data line
12
