Interfaces and Connectors
EPM-32 Reference Manual
43
Watchdog Timer
A watchdog timer circuit is included on the EPM-32 to reset the CPU or issue an NMI if proper
software execution fails or a hardware malfunction occurs.
E
NABLING THE
W
ATCHDOG
Bit D0 in I/O port 1D0h (or 1E0h) is used to enable or disable the watchdog from resetting the
CPU on timer expiration. Bit D1 in I/O port 1D0h (or 1E0h) is used to enable or disable the
watchdog from issuing a NMI on timer expiration. When changing the contents of the register,
make sure not to alter the value of the other bits. The following procedure should be used when
enabling the watchdog to prevent erroneous resets or NMI generation.
The following code example enables the watchdog reset:
MOV
DX,1D2H ;RESET THE WATCHDOG STATUS BIT
IN
AL,DX
OR
AL,04H
OUT
DX,AL
LOOP: MOV
DX,1D0H ;LOOP WHILE BIT D2 (WDOG_STA) = 0
IN
AL,DX
AND
AL,04H
JZ
LOOP
MOV DX,1D2H ;RESET THE WATCHDOG STATUS BIT AGAIN
IN
AL,DX
OR
AL,04H
OUT
DX,AL
MOV
DX,1D0H ;ENABLE THE WATCHDOG (RESET MODE)
IN
AL,DX
OR
AL,01H
OUT
DX,AL
Note:
The watchdog is disabled when the EPM-32 is powered on or reset.
D
ISABLING THE
W
ATCHDOG
The watchdog may be disabled at any time by clearing the above mentioned bits; no special
procedure is required.
R
EFRESHING THE
W
ATCHDOG
If the watchdog timer is enabled, software must periodically refresh the watchdog timer at a rate
faster than the timer is set to expire (1.0 sec minimum). Outputting a 5Ah to the Watchdog Timer
Hold-Off Register at 1D1h (or 1E1h) resets the watchdog time-out period; see page 48 for
additional information. There is no provision for selecting a different timeout period using
software. The following code example refreshes the watchdog:
MOV
DX,1D1H
MOV
AL,5AH
OUT
DX,AL
