Interfaces and Connectors
Bengal (VL-EPMe-30) Reference Manual
43
Power States
CPU power states will affect voltage rails driving DIO circuits as described below:
DIOs and their pull-up resistors will remain powered in all CPU power states (except when
power is turned off).
Power control during CPU power states on user devices connected to DIO lines is
dependent on the application design. These external devices would likely remain powered
unless a power-down mechanism is designed into the system.
Care must be taken when powered DIO signals are connected to un-powered DIO
signals. Significant voltage and current can be leaked from a powered system to an un-
powered system causing unpredictable results. Current limiting and/or diode isolation can
help.
Cables
Cabling issues will affect the usable speed of DIO signals.
These are single-ended drivers/receivers.
Cabling crosstalk can be a problem with fast edge rates. The DIOs are slew-rate limited
and have 50
Ω source terminators to minimize crosstalk and reflections.
SPX Expansion Bus
Up to two serial peripheral expansion (SPX) devices can be attached to the Bengal at connector
J19 using a VL-CBR-1401 or VL-CBR-1402 cable. The SPX interface provides the standard serial
peripheral interface (SPI) signals: SCLK, MISO, and MOSI, as well as four chip selects, SS0#
–
SS3#, and an interrupt input, SINT#.
The +5 V power provided to pins 1 and 14 of J19 is protected by a 1 A resettable fuse.
Table 24: SPX Expansion Bus Pinout
Pin
Signal/
Function
Pin
Signal/Function
1
V5_0
+5 V (Protected)
2
SCLK
Serial Clock
3
GND
Ground
4
MISO
Serial Data In
5
GND
Ground
6
MOSI
Serial Data Out
7
GND
Ground
8
SS0#
Chip Select 0
9
SS1#
Chip Select 1
10
SS2#
Chip Select 2
11
SS3#
Chip Select 3
12
GND
Ground
13
SINT#
Interrupt Input
14
V5_0
+5 V (Protected)
