Valleylab Force 2-2 PCH, Руководство по обслуживанию

Страница: 38 / 74

Power Supply
5-6 Force 2 Service Manual
simply have resistors in series with the opto couplers to limit current.
There are four isolated circuits, each with its own transformer winding for
power.
This generator has three possible RF output receptacles. Single pole,
normally open, high voltage relays make the selection of the receptacle.
The CPU turns on the relays through bipolar drivers on the Interface
board. A CPU controlled delay between relay closure and initiation of RF
drive reduces contact wear. Note the 0.0047 µF capacitors in series with
the RF output and return. These are the primary patient protection
against electrocution and must be high voltage parts.
The REM circuitry measures the pad to pad resistance of dual-pad patient
return electrodes or the wiring resistance of single pad electrodes. A
microswitch in the connector opens for dual-pad patient return electrodes
and selects one of two alarm signal paths in the alarm logic string. The load
on the REM transformer secondary is the measured resistance. The
secondary resonates by two 0.22 µF capacitors, and a synchronous detector
senses the reflected primary load. Four clocked CMOS switches perform
synchronous detection. A potentiometer tunes the oscillator to the
transformer. The detector output amplifies and inputs to four comparators.
Two comparators provide hard wired alarm limits at 5 ohm and 135 ohm
alarm limit for dual-pad patient return electrodes. The third comparator
provides a hard wired alarm limit at 20 ohms for single pad electrodes.
The fourth comparator generates a pulse width modulated waveform by
comparing the return electrode monitor resistance to a triangle wave that
an oscillator generates. The CPU decodes this pulse width to implement
the adaptive REM feature for dual-pad resistances between 5 ohms and
135 ohms.
Power Supply
The high voltage DC power supply on the Power Supply board is an off-
line DC-DC switching converter operating at 80 kHz. A bridge rectifier,
two hold-up capacitors and four power FETs in a bridge configuration
supply the input power. The FETs drive the power transformer T2
primary at 320V peak and varying duty cycles. A 0.75 mH inductor and
two 15 µF capacitors filter the power transformer rectified secondary
voltage which convert a constant amplitude variable duty cycle input to a
variable DC output. A 3526 IC regulator with emitter followers performs
duty cycle control and drives the transformer T3, that switches the power
FETs. The IC contains a sawtooth oscillator, pulse steering logic, and a
comparator. The error voltage on pin 1 varies from 0.5V to 3.5V to change
the output duty cycle. The power transformer has snubber networks to
limit voltage spikes.
Power supply control uses an op amp within the 3526 to amplify the
difference between a feedback fraction of the DC output and a reference
voltage ECON. The CPU generates the reference and the reference scales
as the square root of the front panel power setting. There is a DC current
limit implemented with a comparator and pulse stretcher. The pulse