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2.8
OPERATING MODES
The system controller of the SBC manages register configuration and controls the internal functions. The system
controller is a state machine. The SBC operating modes and the state transitions are shown in Figure 2.8-1. A
detailed hardware characterization of the SBC operating modes by functional block is listed in the following Table
2.8-1
[1.]
Determined by the setting of bits V2C in the regulator control register
[2.]
HVIO availability depends on the device variant
[3.]
Determined by the settings in the relevant HVIO control register
[4.]
See data sheet of the UJA1131HW/3V3,
Fehler! Verweisquelle konnte nicht gefunden werden.
,
section 7.10.4
[5.]
Determined by the settings in the SMPS control register
[6.]
Determined by the setting of bits CMC in the CAN control register
[7.]
Availability of LIN2 depends on the device variant
[8.]
Determined by the setting of bits LMCn in the LIN control register
[9.]
Determined by the settings of bits ENC and ENDC in the fail-safe control register
[10.]
Since V1 is off, EN can only operate as open-drain output in Sleep mode
[11.]
Determined by the setting of bit LHC in the Fail-safe control register
