DNA/DNR-IRIG-650 IRIG Timing Layer
Chapter 3
35
Programming with the Low Level API
Tel: 508-921-4600
www.ueidaq.com
Vers:
4.6
Date: March 2019
DNx-IRIG-650 Chap3x.fm
© Copyright 2019
United Electronic Industries, Inc.
Table 3-1. Event Registers Summary
<event_cfg>
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
EN
DLYC
STPE
EV1IRQ
EV0IRQ
DBL
RPT
EVTPL
Event pulse length in clocks
ISRC
STTE
IRSRC
YM
DM
HM
MM
SM
UM
EDGE
ESRC
1- enable
Delay
1-use
Dual
Repeat
0
Valid for dual events only, PWM
Internal counter
1-use
Internal counter reset source - same codes
as
Year
Day
Hour
Minutes
Seconds
Micro-
Edge
Event source
event,
clock
stop
Issue
Issue
event
mode
mode, event output =1 after subevent0
source selector
start
for the event source, can be used f
or watchdog
mask
mask
mask
mask
mask
seconds
0-falling
0
Disabled
auto-
0=1MHz
trigger
DNA IRQ
DNA IRQ
0-single
0-one-time
and goes back to 0 after subevent1
ISRCM=0:
trigger
implementation or event re-s
ynchronized by
(SB time
ISRCM
mask
1-rising
1
Software only
cleared
1=66/100
M
to disarm
when sub-
when sub-
1-dual
1-repeat
1-13
2-14 66/100MHz clocks
00 - 66/100MHz
to arm
external source, 1PPS, etc
only)
ISRC field
2
BCD time
for single
event
event 1
event 0
1
4
10 - 1 MHz
event
Used when ESRC=4 (will reset internal counter)
clock modifier
3
SB time
events
detected
detected
15
11 - 1KHz
and ESRC=6 (will set time interval for DPLL)
0-Internal
4
Internal counter
ISRCM=1:
1-External
5
DNA bus
00 - PLL
6
DPLL - digital PLL
10 - varies, on CT-650 - 1MHz from TK, synchronized with 1 PPS
7
Reserved
8-31
Digital events
All events are reported as a test IRQ in the main DNA IRQ register (IR_TI, 1<<21)
<event_prm>
WR: various mode-dependent configuration parameters/RD: timestamp capture for the digital events
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
ICNTDIV
Internal counter divider - for the ESRC=4
DPLLF
DPLL frequency (# of pulses between two intervals set by IRSRC source) - for the ESRC=6
SEC
BCD seconds (ESRC=2)
MIN
BCD minutes (ESRC=2)
HR
BCD hour (ESRC=2)
DOY
BCD day of year (ESRC=2)
SBS
Straignt binary seconds of the day for the SB time mode (ESRC=3)
SBY
Straignt binary year for the SB time mode (ESRC=3)
LSA
Layer address (DNA only)
DRD
DWR
DCS
DDL
Y
-# of DNA clocks after read
DNAAV
# of valid DNA address MSBs
DNAA
DNA address
DLAC
DDC
Monitor
Monitor
DNA CS#
or write prior to compare data
0 - ignore address (monitor data only)
1-use
1-compare
DNA
DNA
to monitor
1-14 - select# of valid bits
layer
DNA data
reads
writes
address
TS
Timestamp capture register for the digital events only - stores timestamp that is corresponding to the digital event detection
time
<event_val>
various mode-dependent configuration parameters
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
SBD
Straignt binary day of the year for the SB time mode (ESRC=3)
USEC
Micro seconds (ESRC=2 or 3)
DNADC
DNA data "COMPARE" value - for the ESRC=11
<event_delay0>
Time delay for subevent 0 and output pulse length
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
EVT0DL
Subevent 0 delay after event condition, in 1uS or system clocks (selected in CFG_DLYC)
<event_delay1>
Time delay for subevent 1 and output pulse length
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
EVT1DL
Subevent 1 delay after event condition, in 1uS or system clocks (selected in CFG_DLYC)
STS
Event status register
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
2
0
1
9
1
8
1
7
1
6
1
5
1
4
1
3
1
2
1
1
1
0
9876543210
SEARM
SEVT1
SEVT0
SEVT1D
SEVT0D
ECT
Event counter, reports number of detected events since event was enabled, recycled, cleared if ev
ent is disabled
=1-if event
=1 if
=1 if
=1 if
=1 if
armed
subevent1
subevent0
subevent1
subevent0
counter is
counter is
was issue
d
was issued
active
active
(auto-
(auto-
cleared
cleared
after read)
after read)
