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DNx-AI-208 Analog Input Layer

Tel: 508-921-4600

www.ueidaq.com

Vers:

4.6

Date: November 2013

File:

AI-208 App B.fm

United Electronic Industries, Inc.

Shunting branch R3 instead of R4 to simulate a tensile load gives:

Now that we know how to calculate the theoretical offset on the Wheatstone
bridge output when one of the branch resistances is changed with a known
value, we can compare it with the measured value and get the Gain Adjustment
Factor:

Multiplying each measured values by the “Gain Adjustment Factor” gives us cal-
ibrated measurements.

Vout

Vex

4 Rs

⋅

2 Rg

⋅

-----------------------------------









Eq. 5:

Gaf

VoutCalculated

VoutMeasured

-----------------------------------------

Eq. 6:

Содержание DNA-AI-208

Страница 1: ...r User Manual 18 bit 8 channel 4 and 6 wire Strain Gauge Differential Input Layers for the PowerDNA Cube and RACKtangle chassis November 2013 Version 4 6 PN Man DNx AI 208 1113 Copyright 1998 2010 United Electronic Industries Inc All rights reserved ...

Страница 2: ...50 Also see the FAQs and online Live Help feature on our web site Internet Support Support support ueidaq com Web Site www ueidaq com FTP Site ftp ftp ueidaq com Product Disclaimer WARNING DO NOT USE PRODUCTS SOLD BY UNITED ELECTRONIC INDUSTRIES INC AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS Products sold by United Electronic Industries Inc are not authorized for use as critical com...

Страница 3: ...ation 7 2 3 Configuring the Timing 8 2 4 Reading Data 8 2 5 Cleaning up the Session 8 Chapter 3 Programming with the Low Level API 9 3 1 Configuration Settings 9 3 2 Channel List Settings 10 3 3 Layer specific Commands and Parameters 11 3 4 Using Layer in ACB Mode 14 3 5 Using Layer in DMap mode 16 Appendix A Accessories 18 A 1 DNA STP AI 208 Screw Terminal Panel 18 A 2 Other Accessories 24 A 3 La...

Страница 4: ...ing with the High Level API 7 None Chapter 3 Programming with the Low Level API 9 None Appendix A Accessories 18 A 1 Photo of DNA STP AI 208 Screw Terminal Panel 18 A 2 Pinout Diagram for the DNA STP AI 208 20 A 3 Single Channel Wiring Diagram Full Bridge 20 A 4 Single Channel Wiring Diagram Half Bridge 21 A 5 Single Channel Wiring Diagram Quarter Bridge 22 A 6 Physical Layout of STP AI 208 Board ...

Страница 5: ...s follows Introduction This chapter provides an overview of DNA DNR AI 208 board layer fea tures accessories and what you need to get started DNx AI 208 Layer This chapter provides an overview of the device architecture connec tivity logic and accessories for the DNA DNR AI 208 layer board Programming with High Level API This chapter provides a general overview of procedures that show how to creat...

Страница 6: ...ips are designed to highlight quick ways to get the job done or reveal good ideas you might not discover on your own NOTE Notes alert you to important information CAUTION Caution advises you of precautions to take to avoid injury data loss and damage to your boards or a system crash Text formatted in bold typeface generally represents text that should be entered verbatim For instance it can repres...

Страница 7: ...Half Bridge with ext terminal panel Quarter Bridge with ext terminal panel Bridge resistance 120Ω 350Ω 1000Ω and custom Input impedance 10MΩ in parallel with 50pF Gains 1 2 4 8 10 20 40 80 100 200 400 800 Gain accuracy See Table 1 2 Offset accuracy Temperature drift Offset drift Gain drift 5μV C typ 30ppm C G 1 45ppm C G 800 Shunt calibration Onboard software selectable 256 steps fom 5K to 205K Ex...

Страница 8: ...lock Diagram of DNx AI 208 Device Architecture 1 4 Layer Connectors and Wiring Two D A converters produce excitation voltages The first converter drives exci tation on even numbered channels and the second one to odd numbered chan nels Excitation voltage can be switched on and off on a per channel basis When an AI 208 performs continuous acquisition it applies voltage to the next channel in the ch...

Страница 9: ...n bridges using the S and S terminals In such application situations sensor excitation is usually not required Precise measurement is achieved through the use of more than 8 channels internally in the AI 208 board NOTE For descriptions of connections used with quarter half and full bridge circuits refer to Figure A 3 Figure A 4 and Figure A 5 in the Appendix 1 4 1 Connectors The pinout of the 37 p...

Страница 10: ...r AGND to the ground of the signal source and eliminate the resistors shown in Figure 1 4 for floating differential input signals Input Configuration Type of Input Floating Grounded Typical Signal Sources Thermocouples DC Voltage Sources Instruments or sensors with isolated outputs Typical Signal Sources Instruments or sensors with non isolated outputs Differential Two resistors 10k R 100k provide...

Страница 11: ...trings to select each device subsystem and chan nels to use within a session The resource string syntax is similar to a web URL device class IP address Device Id Subsystem Channel list For PowerDNA the device class is pdna For example the following resource string selects analog input channels 0 2 3 4 on device 1 at IP address 192 168 100 2 pdna 192 168 100 2 Dev1 Ai0 2 3 4 The gain to be applied ...

Страница 12: ...ing sample shows how to configure the simple mode Please refer to the UeiDaq Framework User s Manual to learn how to use the other timing modes session ConfigureTimingForSimpleIO 2 4 Reading Data Reading data from the AI 208 is done using a reader object There is a reader object to read raw data coming straight from the A D converter There is also a reader object to read data already scaled to vol...

Страница 13: ...L 10 enable layer irqs define DQ_LN_PTRIGEDGE1 1L 9 stop trigger edge MSB define DQ_LN_PTRIGEDGE0 1L 8 stop trigger edge 00 software 01 rising 02 falling define DQ_LN_STRIGEDGE1 1L 7 start trigger edge MSB define DQ_LN_STRIGEDGE0 1L 6 start trigger edge 00 software 01 rising 02 falling define DQ_LN_CLCKSRC1 1L 3 CL clock source MSB define DQ_LN_CLCKSRC0 1L 2 CL clock source 01 SW 10 HW 11 EXT defi...

Страница 14: ...for each channel depending on the gain selected and then stretches the settling time as much as possible to utilize at least 2 3 of the time between scan clocks 3 3 Layer specific Commands and Parameters The AI 208 layer has a number of layer specific functions as follows DqAdv208Read This function uses DqReadAIChannel but converts data using internal knowledge of the input range and gain of every...

Страница 15: ...able of providing two sources of excitation voltage Excitation A is connected to even channels and B is connected to odd channels Excitation voltage can be selected and set at any level from 1 5V to 10V This function sets up excitation voltage as close as possible to the requested level and reads it back from the selected channels The user can select either channels 0x10 through 0x17 to read the e...

Страница 16: ...stant Ohms Before the function can measure these parameters specify the measurement conditions ChannelChannel being used for measurements ExcAExcitation level A even channels 16 bit ExcBExcitation level B odd channels 16 bit RaShunt A level 8 bit 256 positions from 0 to 200k RbShunt B level 8 bit 256 positions from 0 to 200k The AI 208 layer has a 14 bit excitation DAC and an 8 bit shunt calibrati...

Страница 17: ...OM sides Now we are going to test device DqAcbCreate pDqe hd0 DEVN DQ_SS0IN bcb Let s assume that we are dealing with AI 208 device dquser_initialize_acb_structure Now call the function DqAcbInitOps bcb Config 0 TrigSize NULL pDQSETTRIG TrigMode fCLClk 0 float fCVClk CLSize CL 0 uint32 ScanBlock acb printf Actual clock rate f n fCLClk Now set up events DqeSetEvent bcb DQ_eFrameDone DQ_ePacketLost ...

Страница 18: ...ELS CHANNELS 1 fprintf fo n printf eFD d scans received d samples min d avail d n size samples minrq avail if avail minrq break STEP 5 Stop operation DqeEnable FALSE bcb 1 FALSE STEP 6 Clean up DqAcbDestroy bcb DqStopDQEngine pDqe DqCloseIOM hd0 ifndef _WIN32 DqCleanUpDAQLib endif 3 5 Using Layer in DMap mode include PDNA h STEP 1 Start DQE engine ifndef _WIN32 DqInitDAQLib endif Start engine DqSt...

Страница 19: ...n dmapout STEP 3 Add channels into DMap for i 0 i CHANNELS i DqDmapSetEntry pBcb DEVN DQ_SS0IN i DQ_ACB_DATA_RAW 1 ioffset i DqDmapInitOps pBcb DqeSetEvent pBcb DQ_eDataAvailable DQ_ePacketLost DQ_eBufferError DQ_ePacketOOB STEP 4 Start operation DqeEnable TRUE pBcb 1 FALSE STEP 5 Process data while keep_looping DqeWaitForEvent pBcb 1 FALSE timeout eventsin if eventsin DQ_eDataAvailable datarcv pr...

Страница 20: ...x AI 208 Analog Input Layer Chapter 3 16 Programming with the Low Level API Tel 508 921 4600 www ueidaq com Vers 4 6 Date November 2013 File AI208 Chap3 fm Copyright 2009 United Electronic Industries Inc ...

Страница 21: ...veral types of bridge configurations full bridge 4 and 6 wire circuits half bridge 3 and 4 wire circuits and quar ter bridge 2 and 3 wire circuits configurations Note that quarter and half bridge configurations require user populated bridge completion resistors Since the panel is supplied with a DB 37 board mounted connector that mates directly with the I O connector on a DNA AI 208 Layer board it...

Страница 22: ...it wir ing diagrams illustrated in Figure A 4 and Figure A 5 Technical Specifications Number of channels 8 Bridge Configurations Full Bridge Half Bridge Quarter Bridge Wiring Schemes Full Bridge Half Bridge Quarter Bridge 6 and 4 wire 4 and 3 wire 3 and 2 wire Operating temperature 20 C to 85 C Operating humidity 90 non condensing Dimensions 4 x 2 5 x 0 7 Bridge Configuration Wiring Scheme Jumper ...

Страница 23: ... Strain Gauge connected to the STP AI 208 panel As the figure indicates you should remove the board mounted jumper when you use a 6 wire Circuit Figure A 3 Single Channel Wiring Diagram Full Bridge S7 20 1 DIO0 EXT_TRIG P7 21 2 S7 AGND 22 3 PS7 S6 23 4 S6 PS6 24 5 P6 S5 25 6 S5 PS5 26 7 P5 S4 27 8 AGND P4 28 9 S4 S3 29 10 PS4 P3 30 11 S3 AGND 31 12 PS3 S2 32 13 S2 PS2 33 14 P2 S1 34 15 S1 PS1 35 1...

Страница 24: ...ridge circuit requires that you solder precision resistors to the board where indicated in Figure A 6 to complete the measuring bridge As an alterna tive you can install precision Resistor Divider Networks in SOT23 packages directly on the board to complete the bridge circuits Figure A 4 Single Channel Wiring Diagram Half Bridge Insert jumper when using a 3 wire connection Remove when using a 4 wi...

Страница 25: ...it requires that you solder precision resistors to the board where indicated in Figure A 6 to complete the measuring bridge As an alternative you can install precision resistor divider networks in SOT23 pack ages directly on the board as shown in Figure A 6 to complete the bridge cir cuits Figure A 5 Single Channel Wiring Diagram Quarter Bridge Insert jumper when using a 2 wire connection Remove w...

Страница 26: ...mpletion resistors or resistor divider packages if required for your application It also shows which terminals to use for making the strain gauge connections for a typical channel Figure A 6 Physical Layout of STP AI 208 Board Solder terminals for external trigger Solder terminals for SOT23 divider Solder terminals for bridge completion resistors Jumper for Ch 3 PSn Pn Sn Sn AGND Ch 1 Plug into Ma...

Страница 27: ...available for the AI 208 layer DNA CBL 37 3ft 37 way flat ribbon cable connects DNA AI 208 to panels DNA CBL 37S 3ft 37 way round extender cable with thumbscrew connectors on both ends connects DNA AI 208 to screw termination panels and other devices DNA STP 37 37 way screw terminal panel A 3 Layer Calibration Please note that once you perform layer calibration yourself the factory calibra tion wa...

Страница 28: ...n of simulating a load on one of the branches of a Wheatstone bridge with a resistor of a known value and comparing the mea sured value to the calculated ideal value The ratio between the ideal value and the measured value is called Gain Adjustment Factor It should be very close to 1 Multiplying the measurement value by the gain adjustment factor compensates for the loss of sensitivity intro duced...

Страница 29: ...gauge resistance and that the R4 branch was shunted with a resistance Rs shunt resistance Figure B 2 Strain Gauge with Shunt Resistance Rs Added ΔVout Vex R4 R4 Rs R3 R4 R4 Rs R4 R3 R4 Eq 3 ΔVout Vex Rg 4Rs 2Rg Eq 4 After replacing R4 with R4 Rs R4 Rs in Equation 1 the voltage output of the bridge when the shunt calibration resistor is enabled is The voltage output change after enabling the shunt ...

Страница 30: ...ensile load gives Now that we know how to calculate the theoretical offset on the Wheatstone bridge output when one of the branch resistances is changed with a known value we can compare it with the measured value and get the Gain Adjustment Factor Multiplying each measured values by the Gain Adjustment Factor gives us cal ibrated measurements ΔVout Vex Rg 4 Rs 2 Rg Eq 5 Gaf ΔVoutCalculated ΔVoutM...

Страница 31: ...istance Semiconductors involved in the shunt calibration circuitry have signifi cant changes in resistance with temperature change To overcome those problems UEI included 25 ppm C 5kOhm 0 1 resistors into shunt calibration circuitry When PS is connected to S on the screw termi nal panel internal circuitry makes it possible to measure voltage drop on one of those precision 25 ppm C resistors thus p...

Страница 32: ...in bold in Figure B 3 A low level API function allows activation and precise measurement of Ra and Rb Once Ra or Rb value is known the value can be inserted into Equation 4 or 5 to calculate the Gain Adjustment Factor B 4 Configuring Framework for Shunt Calibration Flow of operations The shunt calibration will be performed using the following steps Measure bridge output voltage without shunt Engag...

Страница 33: ...aStream double voltageWithoutShunt voltageWithShunt Take one measurement without shunt resistor session Start reader ReadSingleScan voltageWithoutShunt session Stop Turn on shunt calibration for the first channel shunt branch R4 and program the shunt resistance to 100kOhms pChannel EnableShuntCalibration true pChannel SetShuntLocation UeiShuntLocationR4 pChannel SetShuntResistance 100000 0 Take on...

Страница 34: ...asuredDeltaV Turn off shunt resistor pChannel EnableShuntCalibration false Starts the session again session Start Read calibrated measurements double calibratedVoltage reader ReadSingleScan calibratedVoltage calibratedVoltage calibratedVoltage gaf session CleanUp B 6 Shunt Calibration in LabVIEW The following is an example of a typical LabVIEW procedure for performing shunt calibration for strain ...

Страница 35: ...www ueidaq com Vers 4 6 Date November 2013 File AI 208 App B fm Copyright 2009 United Electronic Industries Inc STEP 3 Measure bridge output with shunt enabled STEP 4 Calculate Gain Adjustment Factor STEP 5 Apply Gain Adjustment Factor to measurements ...

Страница 36: ...0 G Gain s 10 Ground Connections 6 H Half bridge Strain Gauge 21 I Input Mode ACB 14 Differential 4 M Manual Conventions 2 Manual Organization 1 Mode DMap 16 P Photo of DNx AI 208 Boards 4 Photo of STP AI 208 Panel 18 Physical Layout of the STP AI 208 23 Pinout 20 Q Quarter bridge Strain Gauge 22 R Resistor divider Networks 21 22 Round Cable 18 S Screw Terminal Panel 18 Screw terminal panels 24 sE...

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