UEi PowerDAQ PD2-AO Series, Руководство пользователя

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Chapter 3: Architecture
25
Digital Output Subsystem
There are eight static digital outputs on the PowerDAQ
analog output board. They are TTL/CMOS output level
compatible, 2000V ESD protected. Due to the static nature
of the outputs they can be updated at any time without any
limitations. Digital outputs provide high current compatibility
(-32/64 ma), which support drive relays or these lines can
be used for control applications.
Digital Input Subsystem
There are eight static digital inputs on the PowerDAQ analog
output board. They are TTL/CMOS input level compatible,
2000V ESD protected. Due to the static nature of the inputs
they can be read at any time without any limitations.
Counter/Timer Subsystem
Depending on your PowerDAQ AO operation mode, the
board can support up to the three DSP based 24-bit
counter/timers with a maximum count rate up to 33 MHz
for 66MHz DSP and 50MHz for 100MHz DSP (PDXI-AO
only) for an internal base clock and 16.5 MHz/25MHz for
the external clock. The minimum count rate is 0.001 Hz for
the internal clock and no low limits for the external clock.
Note For all waveform modes, only Timer0 and Timer1 are
available for use.
Programming of the counter/timer subsystem of the PD2-
AO board requires a minimal understanding of the Triple
Timer Module of the Motorola 56301 DSP. For this
information please refer to the
Motorola DSP 56301 User
Manual
(Motorola P/N DSP56301UM/AD).