ZED-F9P - Integration Manual
UBX-18010802 - R01
2 Hardware description
Page 32 of 64
Objective Specification - Confidential
Figure 30: V_USB connected to VCC
Figure 31: ZED-F9P USB_DM and USB_DP pins
For connecting the debug USB interface to external equipment additional components are required
such as filtering and a connector
Figure 32: External debug USB interface
2.3.9 Display Data Channel (DDC)
An I
2
C compliant DDC interface is available for communication with an external host CPU or u-blox
cellular modules. The interface can be operated in slave mode only. The DDC protocol and electrical
interface are fully compatible with Fast-Mode of the I
2
C industry standard. Since the maximum SCL
clock frequency is 400 kHz, the maximum transfer rate is 400 kb/s.
2.3.10 Antenna supervisor
An active antenna supervisor provides the means to check the antenna for open and short circuits
and to shut off the antenna supply if a short circuit is detected. The Antenna Supervisor is