Ublox SARA-G300, Руководство по системной интеграции

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SARA-G3 and SARA-U2 series - System Integration Manual
UBX-13000995 - R26 Design-in
Page 159 of 217
2.8 General Purpose Input/Output (GPIO)
2.8.1.1 Guidelines for GPIO circuit design
The following application circuits are suggested as a general guideline for the usage of the GPIO pins available
with the SARA-G340 / SARA-G350 and SARA-U2 series modules, according to the related custom function.
Figure 88 describes an application circuit for a typical usage of some GPIO functions of the modules:

Network indication function provided by the GPIO1 pin

GNSS supply enable function provided by the GPIO2 pin

GNSS data ready function provided by the
GPIO3
pin

GNSS RTC sharing function provided by the GPIO4 pin
OUT IN
GND
LDO Regulator
SHDN
3V8 1V8
GPIO3
GPIO4
TxD1
EXTINT0
24
25
R1
VCC
GPIO2
23
SARA-G340 / SARA-G350
SARA-U2 series
u-blox GNSS
1.8 V receiver
U1
C1
R2
R4
3V8
Network Indicator
R3
GNSS Supply Enable
GNSS Data Ready
GNSS RTC Sharing
16
GPIO1
DL1
T1
0 Ω TP
Figure 88: GPIO application circuit
Reference Description Part Number - Manufacturer
R1 47 k
Ω
Resistor 0402 5% 0.1 W Various manufacturers
U1 Voltage Regulator for GNSS receiver See GNSS module Hardware Integration Manual
R2 10 k Ω Resistor 0402 5% 0.1 W Various manufacturers
R3 47 k Ω Resistor 0402 5% 0.1 W Various manufacturers
R4 820 Ω Resistor 0402 5% 0.1 W Various manufacturers
DL1 LED Red SMT 0603 LTST-C190KRKT - Lite-on Technology Corporation
T1 NPN BJT Transistor BC847 - Infineon
Table 58: Components for GPIO application circuit
Use transistors with at least an integrated resistor in the base pin or otherwise put a 10 k Ω resistor on the
board in series to the GPIO.
The ESD sensitivity rating of the GPIO pins is 1 kV (Human Body Model according to JESD22-A114).
A higher protection level could be required if the lines are externally accessible on the application board.
This higher protection level can be achieved by mounting an ESD protection (e.g. EPCOS
CA05P4S14THSG varistor array) close to accessible points.
Any external signal connected to the GPIOs must be tri-stated or set low when the module is in
power-down mode and during the module power-on sequence (at least until the activation of the
V_INT
supply output of the module), to avoid latch-up of circuits and allow a proper boot of the module. If the
external signals connected to the module cannot be tri-stated or set low, insert a multi-channel digital