PAM-7Q - Hardware Integration Manual
UBX-13003143 - R06
Early Production Information
Hardware description
Page 8 of 26
When switching from backup mode to normal operation or at start-up, PAM-7Q module must charge
the internal capacitors in the core domain. In certain situations, this can result in a significant current
draw. For low power applications using Power Save and backup modes, it is important that the power
supply or low ESR capacitors at the module input can deliver this current.
2.5.2
V_BCKP: Backup Supply Voltage
If the module supply has a power failure, then
V_BCKP
will supply the real-time clock (RTC) and battery backed
RAM (BBR). Use of valid time and the GNSS orbit data at start-up will improve the GNSS performance, as with
hot starts, warm starts, AssistNow Autonomous and AssistNow Offline. If no backup battery is connected, the
module performs a cold start at power up.
Avoid high resistance on the V_BCKP line: During the switch from main supply to backup supply, a short
current adjustment peak can cause high voltage drop on the pin with possible malfunctions.
As long as the PAM-7Q module is supplied to
VCC
, the backup battery is disconnected from the RTC
and the BBR to avoid unnecessary battery drain (see
). In this case,
VCC
supplies power to the
RTC and BBR.
Figure 2: Backup battery and voltage (for exact pin orientation, see data sheet)
2.6
Interfaces
2.6.1
UART
PAM-7Q positioning module includes a Universal Asynchronous Receiver Transmitter (UART) serial interface
RxD/TxD
supporting configurable baud rates. The baud rates supported are specified in the
u-blox 7 Receiver
Description Including Protocol Specification
The signal output and input levels are 0 V to VCC. An interface based on RS232 standard levels (+/- 12 V) can be
implemented using level shifters such as Maxim MAX3232. Hardware handshake signals and synchronous
operation are not supported.
2.6.2
Display Data Channel (DDC)
An I
2
C compatible Display Data Channel (DDC) interface is available for serial communication with an external
host CPU. The interface only supports operation in slave mode (master mode is not supported). The DDC
protocol and electrical interface are fully compatible with the Fast-Mode of the I
2
C industry standard. DDC pins
SDA
and
SCL
have internal pull-up resistors.
For more information about the DDC implementation, see the
u-blox 7 Receiver Description Including Protocol
Specification
[2]. For bandwidth information, see the Data Sheet. For timing, parameters consult the
I
2
C-bus
specification
The u-blox 7 DDC interface supports serial communication with u-blox cellular modules. See the
specification of the applicable cellular module to confirm compatibility.
With u-blox 7, when reading the DDC internal register at address 0xFF (messages transmit buffer), the
master must not set the reading address before every byte is accessed, as this could cause faulty behavior.
